A look at the methodology for interpreting the Unified Power Format designs coded in Verilog-AMS, VHDL-AMS or SPICE.
This paper describes a methodology (as implemented in the Mentor Graphics Questa ADMS mixed-signal simulator) for interpreting the Unified Power Format (UPF) for analog mixed-signal designs coded in Verilog-AMS, VHDL-AMS, or SPICE. No changes to the UPF syntax or file are required. A complete implementation and a demonstration of its use in a sample case are provided as proof of concept.
To download this white paper, click here.
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