IP Integration Challenges Increase

Experts at the table, part 3: Lessons learned at advanced nodes applied to older nodes; different views on IP optimization; how engineering teams are changing.


Semiconductor Engineering sat down with Chris Rowen, CTO of Cadence‘s IP group; Rob Aitken, an ARM fellow; Patrick Soheili, vice president of product management and corporate development at eSilicon; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at Synopsys; and Kurt Shuler, vice president of marketing at Arteris. What follows are excerpts of that conversation. Part 1 is here. Part 2 is here.

SE: How pertinent are tools and methodologies developed at new nodes for older nodes?

Rowen: There are a bunch of techniques you build at the bleeding edge that you carry back and which help you at established nodes.

Nandra: We see this, too. The fabs are refreshing 55nm. It’s like a new node. You can put in embedded flash. In fact, some of the things we’ve learned in the foundation IP, like with read and write circuitry, we have backtracked into 55nm. The advantages you get at the most advanced nodes you can put back into older nodes.

Aitken: The way you create a ULP device is that you don’t actually make a higher Vt device, you make a lower Vt device. That way it runs better at lower voltage and gets better performance. It’s a slightly different tradeoff than the LP node, but it produces something that’s better for voltage-scaled operations.

Nandra: This whole segmentation is going to be a little muddier. The way foundries are motivating the use of finFETs with the compact version of 16nm, for example, if you look at the reduced number of masks, that’s going to be very competitive cost-wise with 28nm. That’s going to move some people at 28nm. If it only has three more masks, plus you get all the density improvements and lower power, why not move to finFET technology?

Shuler: Some of the big chipmakers have their own foundries. They need them to get to the next node. But will their next products be better because they have the design team in-house working closely with the fab team?

Soheili: Momentarily, maybe. But it’s actually a burden to be stuck with the kind of expense and that kind of market position. Something may be competition to their own products so they can’t take the business. It has pros and cons for sure. The cost of just developing it, and then filling the fab, is a problem.

Rowen: It’s never been more expensive to run a fab.

SE: What used to happen at older nodes is you could develop a chip and it would run across that process at multiple foundries. Now you have to commit to what is often version 0.01 of a process, and it may change radically for every foundry. What’s the impact of that?

Aitken: We observed this happening and we said we cannot work early enough with the foundries to get answers to the questions we have. So we actually hired some device physicists as modeling people and talked to the equipment vendors to figure out what the next node will have to be. There are certain aspects that are required, based upon what geometry you want to get, what area scaling you want to get. And by doing that we were able to conjure up what amounts to a predictive technology set that we can use to roughly characterize. It’s obviously imperfect, but it does give us a general idea of what a node will look like. We’ve been able to look at that at 14nm, 10nm and 7nm, and predict what they probably will get. So when we get to version 0.001, it’s not a surprise to us. It also identifies places where they’re going to have trouble. Something may be an aspiration rather than a real number.

Soheili: In the 1990s when I worked at another chip company, we had process engineers living at TSMC. We sent 20 or 30 of them, and they were there for months to get this kind of an insight. All of your assumptions about IP come from a system, so as things change over time you’re in bad shape. It’s a huge burden. You sit down with the foundry and say you’ve got a customer and need to get specific IP on early because it has to tape out in 18 months. What do you need to do?
It’s a huge challenge.

Nandra: It’s coming down to the point where the customer has huge leverage over the foundry—that’s the PDK they want to use. Everything we suffer from, the SoC developer suffers from on the customer side. If they dictate that they’re going to use a particular version of the PDK, the IP has to be developed on that version. It makes things a lot simpler. But if you have the ability to run qualification vehicles before you pick out the IP, that’s really good because it gives you some insights into the way the technology is going. But it does take a different type of designer to work with an unstable PDK. You have to sometimes remove a level of noise on the update because it doesn’t impact your design. And other times you need to recognize that’s really going to affect your design. It takes a really seasoned engineer to do that.

Aitken: You also have to train them to not over-optimize. So if you get the last picosecond out of version .01 of a PDK you’ll be very disappointed when version .05 comes out.

Nandra: That’s an interesting challenge for the customer. They always say, ‘You haven’t optimized the IP enough.’

Rowen: But that’s also part and parcel of how the IP industry is evolving to really serve the problem. The ocean is not smooth and placid all the time. There is inherently a lot of churn taking place. Relative to the problem faced by a fabless semiconductor company trying to do the same thing, the leading-edge IP companies are very well positioned to develop a critical mass of methodology and know-how to be able to make sound economic and technical decisions. So at what pace do you track?

Nandra: And we’ve removed one of the variables, which is standards-based IP. We know that no matter how much you change specs, the standard is going to be maintained regardless of the process technology.

Rowen: Mixed in with this is a marketing decision about which variant—is this more optimized for power, is it more optimized for performance?

Nandra: We focus on the PPA, but the standards we’re addressing are defined by a standards committee.

Aitken: I’ve gotten to the point where I say there is no scale factor. If you say your processor ran at this speed using this much power at this node, there is no magic number to say what it will be at the next node. You have to say what you want it to be. You can have it 30% smaller or 50% faster or 10% lower dynamic power. You can move these numbers around quite a bit. Having the IP flexible enough to allow the implementation team to make those tradeoffs is a big part of the delivery challenge.

Nandra: If you maintain the same PPA as the previous technology node, you’re not going to get any business.

Aitken: Yes, but the question is what they want, which is where the big.LITTLE idea came from. ‘We want to get to low power when we get to the next node, but we also want really good performance.’ So you have to use one core for one thing and another core for something else.

SE: At advanced nodes, processes are much different from one foundry to the next. How do you account for that in your IP development?

Nandra: We make the IP available across all the processes and let the customer decide where they want to fabricate their SoC.

Soheili: The customer has something to do with this, as well. At some point they’re going to call you in and say, ‘This is where we’re going to go.’ They’re as much interested in getting the ecosystem up and going and ready for them as you want them to be. There are lots of backroom conversations like that.

Rowen: It’s about relationships. The kind of communication you have with your customer allows you to both be a trusted partner in these discussions. So they ask the implications if they did A or B or C, and you can contribute to that. Also, it allows you to become familiar with their thought process and their set of problems so you can anticipate what decisions they may make. We often run into situations where customers ask for several things. We look ahead and try to figure out what they’re really asking for so when they look for something new we’ve already thought through the issues. It’s very much about being closely engaged with them on both a technical and business level.

Aitken: It’s less of an issue for IP providers than the foundry business. If you have a very small number of very large customers, they have a very large influence on you. When you’re spending $15 billion on your next-generation fab, it’s important.

Soheili: And those customers talk to three or four fabs, so it’s no surprise that the center of the processes are so tightly correlated with each other.

Shuler: Everyone wants to commoditize their suppliers if they possibly can. That’s what gives them leverage.

SE: Given all the changes underway, has the makeup of teams developing IP changed?

Rowen: In some ways, very much so. If we look back at Cadence a few years ago, it was a sophisticated EDA and IP company, but not really a systems company. Part of my mission is to be able to get into the head of the system designer to figure out what they really care about, what are the optimization dimensions they care about, and how they are going to optimize at the software level for power, size, performance and versatility. We have to figure out where they’re going and what we need to do to demonstrate relevance. All of us are becoming more sophisticated at the systems level in understanding what is the end purpose. On top of that, you have much more involvement in the device physics and in tracking different standards. It’s no longer just IEEE standards. It’s automotive standards, IoT standards, and where do we make our investments. Some of these investments are long-term investments. You have to be there, investing before the customers know they’re going to go there.

Soheili: When the circuit designer is looking at finer geometries and anticipates what he can and cannot do and the number of layout people involved—just the enormity of the task—from every dimension the business feels like the move from one node to the next is not a linear jump. When we place and route an ASIC at 65nm, we spend 4.5X that number at 28nm, and even more at 14nm. It has impacts on all aspects of the business.

Aitken: Moving up in the stack we have software people who are concerned about how products are built and interact with each other. At the low level we have people who worry about where band gaps are. And in between we have people focused on operations and efficiency. If we just do what 10 guys in a barn used to do and try to scale that up to the kind of operation we have now, it doesn’t work. There aren’t that many people in the world who know how to do this stuff. We have to automate and provide underlying IP systems that allow our people to be as productive as possible. You can’t do everything at the same time just by adding a new person every time a new problem comes along.

Shuler: If you look at the difference between our engineering team today versus what it was a few years ago, as we’ve expanded the scale and scope of offerings, what’s changed is we’ve got people doing architecture and in the CTO office figuring out which markets we’re going after and being very specific about shooting arrows in the right direction. We also have more software people because a lot of that goes with the integration and ease of use. Verification is a greater proportion of people, as well, including formal and methods. It’s not just a bunch of RTL developers.

Nandra: We have more than 2,000 people doing IP today. Setting up a common infrastructure has been paramount. We have a strong initiative to improve efficiency. The key here is system knowledge. You really need to understand what your customers are going to do now and in the future and have a team that’s responsible for all the logistics.