Just because IP complies with a spec doesn’t mean it can’t be tweaked. But what happens if you do tweak it?
Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things:
These developments haven’t gone unnoticed by IP vendors, of course. In technology, broad-based engineering issues are considered opportunities. But solving them isn’t so simple.
“There are two vectors we see,” said Steve Roddy, Xtensa product line group director at Cadence. One is much more pressure on IP vendors to customize IP or build in customization. If you look at interface IP, there was one implementation five years ago. Now with PHYs you have a tremendous amount of logic, soft IP, and it’s being rapidly customized. Basically what you need is an IP factory. The second vector is there is always something around IP, so as a vendor you need to provide more of a reference design or a starting point. This is not just about assembling multiple pieces. IP customers are looking for starting points and application-specific reference points.”
That knowledge transfer is becoming a critical part of selling IP, as well. “This is a recognition that system optimization is more than just a tinker-toy assembly,” Roddy said. “If you have 23 IP blocks and you tweak the parameters on a DDR controller or processor, these are the characteristics you will get. So one customer may be focused on a killer image quality while another is focused on cost and another on battery life—all with the same IP. That also requires more SystemC modeling, prototyping and emulation so you can put all of this stuff together and tune it.”
While Cadence’s purchase of Tensilica landed it squarely in the customizable IP space, but others are moving in that direction, as well.
The large semiconductor manufacturers often lead (and in fact sometimes drive) the market definition of IP,” said John Koeter, vice president of marketing of IP & Systems at Synopsys. “To be able to successfully work with these market makers, a deeper collaboration is necessary. This often manifests itself in early development of new features, as well as early development on new process technologies.”
Koeter said that 50% of Synopsys’ IP revenue now comes from the top 20 semiconductor manufacturers. That market is growing rapidly, too. Gartner Dataquest estimates the third-party IP market is now $2 billion and growing more than 10% a year. And for the most part, because the IP market is consolidating and there is a tighter relationship between IP vendors and customers, there also is a better understanding about how IP will be used by the large chipmakers. But there are hiccups along the way.
“There can be some challenges, particularly in areas like the I/O ring, test methodologies clock, reset, and power management logic, and timing constraints,” said Koeter. “Synopsys works very closely with our customers to prevent these issues from manifesting themselves. For example, we offer initial design kickoff reviews, periodic integration reviews and signoff meetings to catch any problems well before tape-out.”
Arteris, whose business model is based on connecting various pieces of IP through a network-on-chip fabric, sees much of this problem firsthand. “There are a lot of variables to work with configurable IP,” said Kurt Shuler, the company’s vice president of marketing. “Even some of the stuff we call ‘jellybean’ is configurable, such as Bluetooth. It’s well-defined and it conforms to standards, but if you compare the price and performance of one piece of standard IP to another it’s not a 100% apples-to-apples comparison or they wouldn’t be able to differentiate.”
More data, less data
One of the big opportunities for IP in the future is with stacked die, whether it’s 2.5D, 3D-IC or some variant of that. In stacked die, IP that is developed at one process geometry doesn’t necessarily have to be migrated to the next node. It also can be characterized more independently and physically separated or move into closer proximity. But it also opens up some new challenges that haven’t been dealt with by most companies.
“A lot of the 3D work has been hampered by a lack of standards,” said Mike Gianfagna, vice president of marketing at eSilicon. “Today if you want to characterize IP, there are interfaces you understand. You conform to the interfaces and test and you see how they work together. That’s not true in 3D. You may have conformance at the on-chip level, but not at the off-chip PCB trace level. There are a whole bunch of standards needed for this. It will get better over the next few years, but in the interim it’s like the Wild West.”
Exacerbating this lack of standards is that IP created for stacked die is new—not all of the existing IP will work in these new packages and architectures. That means not all of the IP will be ready at the same time.
“Right now when you look at IP it’s tried and proven,” said Gianfagna. “That’s not true with stacked die.”
But even what’s proven to work in some designs brings a level of uncertainty for other designs. And there is so much data to wade through that it can be overwhelming for design teams that already are under pressure to bring increasingly complex chips to market—one of the main reasons they are buying third-party IP in the first place.
“There is an explosion of data,” said Karim Khalfan, technical marketing manager at Cliosoft. “In fact, one of the issues we’ve been helping customers solve is how to reduce disk space. As we go down nodes, the size of data increases. This problem is well known for the really big chipmakers, but it’s also a problem for smaller ones. Some of our customers have 20 to 50 people. We’re seeing more and more questions from them.”
Cataloguing IP has only really just begun for a lot of this data, said Khalifan. The problem with cataloguing, though, is that it has to be aggressively maintained like any database. That’s a time-consuming task, even though ultimately it can save engineering teams time and aggravation.
Another option is to, in the words of ARM CTO Mike Muller, “use bigger LEGOs.”
“As an example, our customers want to buy a fully functional, integrated USB port or DDR subsystem versus individual pieces of IP,” said Synopsys’ Koeter. “Some estimate that it costs as much to integrate IP as it does to license it in the first place. This is a win-win for both the customers and Synopsys—faster time-to-market, less risk, and less integration. That leads to lower overall costs and enables customers to focus on their core competencies.”
This has been argument for subsystems and ultimately third-party platforms in stacked die. So far they are slow to take off, but the consensus across the IP world is that this shift is inevitable as chipmakers continue to wrestle with complexity, time-to-market pressures and the need to cut costs.