Knowledge Center

Knowledge Center

A brief history of design

We start with schematics and end with ESL


From an EDA perspective, modern history starts with a schematic representation of the design. This was a gate level design with explicitly defined interconnect. It bore a lot of similarities to printed circuit board techniques that had preceded the design of integrated circuits and thus the technology was fairly mature. This was also the birthplace for the original three large EDA companies Daisy, Mentor and Valid. Textual forms of the schematic also existed called a netlist. Most early hardware description languages (HDL) were of this form.

As design sizes grew, schematics became unwieldy. In the early 80’s hardware description languages started to emerge. The most important of these was Hilo, developed at Brunel University in England. It defined what is now considered as the essential element of a register transfer language – a clock edge and the associated computation that should happen as a result of that clock. The timing of those events was unspecified and it was left to a separate process to work out if everything could happen within the defined clock period.

The next stage in the development of RTL was the Verilog language defined by Gateway Design Automation. RTL was mainly used as a way to verify the design and a primarily manual transformation to the gate level was necessary. This suppressed the rate at which the technology was adopted.

In the late 80’s, a new company emerged, Synopsys that had an automated way of synthesizing a gate level description from RTL. Synopsys’ Design Compiler accepted Verilog, now owned by Cadence, as its input language and the first RTL flow had been created. While many improvements have been made in the flow over the next 25 years, it remains essentially the same flow and Synopsys dominated the RTL synthesis market.

In the 2010’s a higher level of abstraction was becoming necessary. This is generally referred to as the electronic system level (ESL). While productivity is the principle reason for this, the additional speed of design comes from being able to define a system faster using more abstract languages, that they are easier and quicker to verify and that it allows more time to be spent in architectural exploration so that better implementation can be found.

In 2014, the major players in the high-level synthesis market are Cadence, who recently bought Forte Design Systems and Calypto that has the high-level synthesis technology developed within Mentor Graphics. While a separate company, Calypto is 51% owned by Mentor.


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