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A brief history of logic simulation

Important events in the history of logic simulation
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In the 1970s, most simulation was at the gate level and primarily used for board level simulation. Commercial simulators included Lasar from Teradyn and Tegas. In 1981, Hilo was created by Brunel University in England and commercialized by Cirrus Computers. It was the first true RTL simulator although the term had not been coined at that time. Hilo 2 was a combination of a logic simulator, fault simulator, min-max timing simulator. Early logic simulators had waveform languages that looked very much like tester languages and thus most of the simulators at this time finished up being acquired by tester companies. For example, Cirrus Computers was acquired by GenRad in 1983.

Phil Moorby, one of the creators of Hilo 2, left GenRad and started to work for Gateway Design Automation. In 1984 he created the Verilog hardware description language (HDL). This was the first simulator that supported some of the capabilities required to do chip simulation. In 1990 Gateway was purchased by Cadence Design systems.

In 1981 a U.S. Department of Defense (DoD) program was proposed called the VHSIC (Very High-Speed IC) program. In 1986 the HDL developed in this program was offered to the IEEE for standardization. It was called VHDL (Vhsic HDL). It became IEEE standard 1076-1987.

In response, Cadence started to open up the Verilog language and in 1990 created Open Verilog International (OVI).

The two languages fought a bitter battle that has been said to have been the most costly mistake in EDA history. Verilog in the most popular language today although VHDL is still in use.

The most popular verification methodology in use up until this time was termed directed verification. Each test was directed at exercising certain aspects of a design. A new technology had been developed within Sun Microsystems that used randomization in the creation of stimulus. The language used to do this was called Vera and was commercialized by System Science Inc. System Science was bought by Synopsys in 1998. The methodology surrounding this was known as constrained random test pattern generation.

In the late 90s Co-Design Automation started working on a set of extensions to Verilog that they called SuperLog. Co-Design was bought by Synopsys in 2002 and parts of SuperLog were used in the creation of SystemVerilog. In addition, many aspects of Vera were rolled into SystemVerilog.


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