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DFT and Clock Gating

Insertion of test logic for clock-gating
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Description

Design for test (DFT) is also important in low-power design. To increase test coverage, ensure that the clock-gating logic inserted by the low-power engine is controllable and observable. First, select a clock-gating cell that contains test control logic, indicating whether the test control logic is located before or after the latch. The figure depicts the possible location of test control logic.



Then, specify the test control signal that must be connected to the test pins of the integrated clock-gating cells, and connect the test signals. There are two scenarios to connect the test pins of the clock-gating logic:
Set up observability logic prior to mapping: If the control signal is specified before synthesis starts, the RC low-power engine can connect the signal to the test enable pin of the clock-gating logic during clock-gating insertion.
Insert the observability logic after mapping: If the control signal is specified after the design is already synthesized, there are commands to connect the test signal at that stage.



Page contents originally provided by Cadence Design Systems


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