Techniques that reduce the difficulty and cost associated with testing an integrated circuit. This can result in a decrease in the time spent on a tester, a decrease in cost associated with generating the test vectors or in the design iterations necessary to achieve acceptable test coverage or yield.
Some techniques are very simple, such as supplying resets into a design. Without these, the test vectors must enact a homing sequence that brings a design into a known state such that testing can actually begin.
More typically it includes the introduction of scan-based testing, built-in self-test (BIST) or increased observability using JTAG. Most test circuitry is inserted post synthesis although BIST techniques are often integrated into the block's functionality.
Early analysis can be performed during the RTL design phase to identify design decisions that may affect the testability of the design.