Double patterning is a common multiple patterning technique. Today’s single-exposure, 193nm wavelength lithography reached its physical limit at 40nm half-pitch. Multiple patterning enables chipmakers to image IC designs at 20nm and below.
Typically, double patterning refers to the litho-etch-litho-etch (LELE) pitch-splitting process in the fab, according to Mentor Graphics. Double patterning also includes a spacer technique called self-aligned double patterning (SADP).
In the fab, LELE requires two separate lithography and etch steps to define a single layer. LELE provides a 30% reduction in pitch, according to Sematech. But LELE can be expensive, as it doubles the process steps in the lithography flow. Initially, this technique separates the layouts that cannot be printed with a single exposure, forming two lower-density masks. Then, it uses two separate exposure processes. This, in turn, forms two coarser patterns. They are combined and superimposed, which enables a single finer image on the wafer.
Double patterning also imposes new layouts, physical verification and debug requirements on the designer. For example, on the design side, the mask layers are assigned colors, based on spacing requirements. The mask layers are split, or decomposed, from the original drawn layout into two new layers.
One key methodology decision is as basic as whether or not you want the designers to see colors at all—called a “colorless” design flow. The alternative is a two-color flow, in which the designer tapes out two masks, choosing one of several decomposition options. Of course, there are trade-offs with any design flow.
At 20nm, foundries are using several different double patterning design flows. One of the more common flows does not actually require the design team to decompose their layers into two colors. However, there are situations in which the designer may want to know what the color assignments will be. As reasonable as this may sound, seeing the double patterning colors will most likely degrade debug productivity.
The use of stitching can greatly reduce the number of double patterning decomposition violations that a designer has to resolve. However, stitching also adds significantly increased complexity—the decomposition tool must process many additional design rules to generate legal stitches and know how to use them properly during coloring. The initial challenges to automating stitch generation and layer decomposition are: 1) capturing these constraints within the syntax of the tool language, and 2) adhering to the complex combination of rules.
One of the biggest challenges in double patterning design is understanding and debugging violation loops. Unlike DRC errors, errors often have multiple solutions. Of course, the problem with multiple options is that not all options are created equal—some are better choices than others.
Meanwhile, SADP or spacer is another double patterning technique. SADP, which has been used to extend NAND flash memory to the 1xnm node, is now moving into logic.
The SADP process uses one lithography step and additional deposition and etch steps to define a spacer-like feature. In the SADP process, the first step is to form mandrels on a substrate. Then, the pattern is covered with a deposition layer. The deposition layer is then etched, which, in turn, forms spacers. Finally, the top portion undergoes a chemical mechanical polishing (CMP) step.
Simple patterns, including those in flash memory or the fins in finFETs, are done in SADP or another version of the technology, self-aligned quadruple patterning (SAQP). In both techniques, lone parallel lines are formed, followed by cuts.
Metal levels in DRAM and logic chips are more complex and can’t be done with SADP or SAQP. These metal layers require LELE. SADP and SAQP also have less design flexibility than LELE. Hole-type patterns are required LELE-type technology.