Hard IP can be viewed as the set of masks necessary to fabricate a piece of a chip that can be integrated into a larger device. Typically analog blocks or devices such as a SERDES are delivered as hard IP. When this type of IP is delivered it will most likely be as a set of GDSII files.
Along with the layout, the IP developer would also need to provide a timing model for the IP, possible a SPICE model so that detailed simulation can be performed, an IBIS model for signal integrity simulation, models for testability etc. In addition a functional Verilog or VHDL model will be required for integration of the device into the SoC.