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Layout versus Schematic Checking

Device and connectivity comparisons between the layout and the schematic
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Description

A layout vs. schematic (LVS) physical verification tool performs a vital function as a member of a complete IC verification tool suite by providing device and connectivity comparisons between the IC layout and the schematic. An LVS tool enables accurate circuit verification because it is able to measure actual device geometries across a full-chip for a complete accounting of physical parameters. The measured device parameters supply the information for back-annotation to the source schematic and comprehensive data for running simulations.

LVS tools are commonly used with parasitic extraction tools for measurement of device stress parameters (especially at 40 nm and below), for electrical rule checking, and to interactively make corrections to reduce error debugging time.

Performance improvements in LVS tools are achieved through hierarchical processing, that is processing a repeated block only once, and hardware scaling, or the ability to divide the LVS job across many CPUs.

A graphical environment associated with an LVS tool may provide design-fix suggestions and visual indication of the location of geometrical and electrical violations, such as shorts in the layout. Cross-probing refers to the ability to provide a direct correlation between the physical layout and a SPICE netlist to aid in debugging. A dynamic results-viewing environment allows designers to see violations and start fixing them as soon as they are detected, rather than waiting until a design rule check (DRC)/LVS run completes.

The hierarchical methodology can be enhanced with technology that automatically scans for repeated, common device patterns, even if the patterns are not explicitly defined in the design database. Identifying inherent repetition, this technology introduces or “injects” hierarchy to simplify the design and speed the comparison process.

LVS tools can also provide automatic device recognition and parameter extraction for standard devices described by typical BSIM3/4 and PSP parameters. Some tools include a user-defined option when more complex or unique models are needed. At 40 nm and below, foundries define device parameters that are unique to their manufacturing process. Some of these parameters may be a function of relationships among multiple transistors.

The LVS process can be enhanced with a programmable electrical rule checker (ERC), which uses customer-defined electrical rule checks to automate error-prone manual checking. A programmable ERC capability recognizes grouped devices that are connected per the users’ definition and measures geometrical data associated with the identified circuit topology. The combination of LVS and programmable ERC can be used to find design errors not detectable by LVS alone.

Page contents originally provided by Mentor Graphics


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