Photolithography is a patterning process in chip manufacturing. The process involves transferring a pattern from a photomask to a substrate. This is primarily done using steppers and scanners, which are equipped with optical light sources. Other forms of lithography include direct-write e-beam and nanoimprint. There are also several next-generation lithography (NGL) technologies in R&D, such as extreme ultraviolet (EUV), multi-beam e-beam and directed self-assembly (DSA).
As Moore’s law has driven the semiconductor technology roadmap below 1 µm, a steady stream of new technologies has been required to produce leading edge chips. For most of that roadmap, the enabling engineering solutions were on the processing side. For instance, the development of i-line, then KrF and ArF light sources, advanced resist chemistries, etc.
As we continue to shrink the pitch, we also push the lithography k1 (which indicates the difficulty of the litho process) lower and we are currently stuck with 193nm/1.35NA scanners. When k1 dropped below 0.6, the scanner alone could no longer resolve the images on the wafer, and new EDA software had to be developed to compensate for the lost resolution. This software began with rule-based optimal proximity correction (OPC), and as we continued down the curve, we added model-based OPC, sub-resolution assist features (SRAF), and similar techniques.
This extended the use of lithography tools and because the adjustments were applied post-tapeout (during the mask preparation phase), the designer didn’t have to know about them.
At 20nm, k1 dips below 0.25, and a whole new kind of technology, double patterning, is required. The trend continues with 14nm requiring triple patterning or spacer assisted double patterning (SADP). In fact, even if the initial EUV scanner capability arrives for 11nm, we may still need double patterning for some layers using EUV.
Unlike the introduction of OPC, which did not require the designer to be involved, double patterning (DP) solution will impose new layout, physical verification, and debug requirements on the designer.
Consider the increase in resolution capability that was enabled at each node. For the 90, 65, and 28nm nodes, most of the increased resolution came in the form of new scanner capability. For the 45 and 20nm nodes, almost all of the increased resolution comes from software-based solutions. Some of this software and extra work is “creeping” into design.
This migration of manufacturing requirements into design started with a few suggested activities at 65nm, such as recommended rules compliance, lithography checks, and critical area analysis (CAA). At 45nm, some of the lithography simulation checks became required. At 20nm, double patterning, lithography simulation, and smart fill are required, and CMP simulation, CAA, and recommended rules compliance are heavily promoted.
Original Content provided by Mentor Graphics