Upsizing improves slew times, reducing dynamic current. Downsizing reduces leakage current. To be effective, sizing operations must include accurate switching information.
In design with low-power intent, synthesis tools automatically perform a variety of power optimization techniques, including logic resizing.
By removing a buffer to reduce gate counts, logic resizing reduces dynamic power. In the figure, there are also fewer stages; both gate count and stage reduction can reduce power and also, usually, area.
On a sample of designs, logic resizing reduced dynamic power by less than 5% but could also reduce area by up to 10%. It had no significant impact on any other aspects of the design flow.
Page contents originally provided by Cadence Design Systems