Knowledge Center

Knowledge Center

Low Power Methodologies

Methodologies used to reduce power consumption.
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Description

Power has become the gating factor in many designs below 40nm on a variety of fronts, ranging from leakage current at 28nm and 20nm, and again at 7nm; dynamic power density at 16/14nm using finFETs; and at thermal effects caused by power. On top of that, there are related issues such as electromigration and electrostatic discharge.

There are a number of approaches that have been gaining favor to deal with power. One is to completely change out the materials, replacing bulk CMOS with fully depleted SOI. Another is to replace the materials in the vias at the most advanced nodes—7nm and below—to address the resistance and capacitance of electrons moving through skinny wires, otherwise referred to as RC delay.

Other techniques have been added as well, such as forward and reverse biasing in FD-SOI, near-threshold computing whereby a processor of any sort performs some compute function before the device is fully powered on.

There also are techniques for reducing power across a system, keeping logic elements in the "off" state most of the time; setting up individual power rails for certain functions so the entire chip doesn't have to be turned on; and even reducing the accuracy of the computing across a number of compute elements working in some synchronized fashion, such as a neural network.


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