The semiconductor manufacturing process is often split into two sub-categories. Front-end-of-the-line (FEOL) is where the transistors are created and backend-of-the-line (BEOL) is where the interconnects are formed within a device. Interconnects, the tiny wiring schemes in devices, are becoming more compact at each node, causing a resistance-capacitance (RC) delay in chips.
In a device, there are two types of BEOL interconnect wires: intermediate and global. Intermediate wires provide the lower-level connections in a device. The problems associated with RC delay reside with the global wires, which connect the intermediate layers. Adding to the complexity is that chipmakers have inserted another wiring hierarchy starting at 20nm. The scheme, dubbed the middle-of-the-line (MOL), involves the local interconnects in a design.