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Knowledge Center

Multi-Corner Multi-Mode Analysis

Increasing numbers of corners complicates analysis. Concurrent analysis holds promise.
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Description

At advanced technology nodes variability has become a big challenge for designers with the growing number of modes and corners. IC physical design tool problems are amplified at leading edge nodes because designs must be concurrently optimized for a growing number of modes and corners. With most tools, top-level closure for timing, signal integrity, power, and manufacturing design rules requires a separate abstraction model for each mode/corner scenario. The common workaround is to run fewer scenarios with increased timing margins. The cost of this approach is slower time-to-market, increased die size, and greater power consumption, which make products less competitive.

For example, problems can arise when trying to close chip-level timing if the analysis tool cannot address all the modes, corners, power states, and complex clocking concurrently. To save time, block-level implementations are often analyzed only for “best case/worst case” functional timing. However, at sign-off some mode and corner combinations may not meet requirements, and designers must then fix these cross-corner or cross-mode violations through time-consuming ECO loops before the chip can tape out.

Full-chip static timing analysis typically requires a separate extraction run for each design corner, and a separate analysis run for each corner/mode combination. The results must then be manually analyzed and fixed in each partition, then re-checked with chip-level extraction and analysis. Fixing a violation in one timing scenario is likely to cause a new violation in another. This situation gets even more complex when power needs to be optimized along with timing, as the worst case power corner could be different from the worst case timing. For advanced designs the number of mode/corner combinations might be in the hundreds.

“Multi-corner multi-mode” (MCMM) denotes the ability of a design tool to optimize for all design metrics across all modes and corners concurrently. This is accomplished using a data structure called a virtual timing graph. To represent mode/corner scenarios, multiple virtual timing graphs are generated, and then stored as a single vector-based timing tree that simultaneously captures information for an unlimited number of mode/corner combinations.

Original page contents provided by Mentor Graphics


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