This test concept replaces the notion of testing each chip individually, instead, using the tester to test multiple dies at the same time. But it is not quite as simple as it sounds and the efficiency of the system has to be kept high. Efficiency in this regard is the increase in time taken to test multiple cores compared to the time taken for a single core. Early examples of its usage were on pure digital chips, such as memory.
Multi-site testing is made more difficult when the chip being tested contains any analog circuitry or when functional vectors are required. These can cause divergent flows in the test program which impacts efficiency.
There are several strategies used to perform this. The tester can provide dedicated hardware for each device-under-test and while this may achieve higher efficiency, it will also be at higher costs. Alternatively, the tester may contain a single computer that uses multi-threading, each thread associated with a single chip. Yet another approach arranges phases of the test serially so that a resource can be shared.