For power-down, a specific sequence is generally followed: isolation, state retention, power shut-off. For the power-up cycle, the opposite sequence needs to be followed. The power-up cycle can also require a specific reset sequence.
Given that there are multiple—possibly nested—power domains, coupled with different power sequences, some of which may share common power control signals and multiple levels of gated clocks, the need for verification support is tremendous. The complexity and possible corner cases need to be thoroughly analyzed; functional and power intent must be analyzed and thoroughly verified together using advanced verification techniques.
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