In certain cases, the state of key control flops needs to be retained during poweroff. To speed power-up recovery, state retention power gating (SRPG) flops can be used. These retain their state while the power is off, provided that specific control signaling requirements are met.
Cell libraries today may include such special state retention cells. A key area of verification is checking that these library-specific requirements have been satisfied and the flop will actually retain its state.
To implement power gating, special state retention cells are required to store prior state(s) of the blocks before power-down. The basic flip-flop has been modified in SRPG, and the master latch runs on the same power supply Vdd as combinational logic, while the slave latch runs on the different power supply Vcc. The state of the system will be retained in the flip-flops during power down and all the combinational logic will be turned off during sleep mode.
State retention registers require two types of power supplies: a switchable power supply and an always-on power supply. This introduces some complications and penalties in power routing area requirements. The physical designer, or implementation tool, must allocate extra area to accommodate this additional power routing.
The advantages of SRPG include shutdown leakage savings, which can be independent of process variations. It allows for faster system power-on because the state is preserved in the slave latch.
Disadvantages include increased area and die size; timing penalties such as increased signal and clocking delays; increased routing resources (power routing for Vcc and a power-gating signal tree with on buffers); specialized library models for SRPG cells; additional power overhead in the active mode; and impacts to functional verification, physical integration, and DFT.
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