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Knowledge Center

Process Power Optimizations

power optimization techniques at the process level
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Description

Multi-Vth: With the use of multi-threshold libraries, individual logic gates use transistors with low switching thresholds (faster with higher leakage) or high switching thresholds (slower with lower leakage).

Substrate biasing (bodybiasing or back-biasing): Substrate biasing in PMOS biases the body of the transistor to a voltage higher than Vdd; in NMOS, to a voltage lower than Vss.

Page contents originally provided by Cadence Design Systems


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