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RTL Power Optimizations

Optimization of power consumption at the Register Transfer Level
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Description

There are many techniques for power management, including:

Clock tree optimization and clock gating: Portions of the clock tree(s) that aren’t being used at any particular time are disabled.

Operand isolation: Reduce power dissipation in datapath blocks controlled by an enable signal; when the datapath element is not active, prevent it from switching.

Logic restructuring: Move high switching operations up in the logic cone, and low switching operations back in the logic cone; a gate-level dynamic power optimization technique.

Multi-Vth :With the use of multi-threshold libraries, individual logic gates use transistors with low switching thresholds (faster with higher leakage) or high switching thresholds (slower with lower leakage).

Multi-supply voltage (MSV or voltage islands: Selected functional blocks are run at different supply voltages.

Dynamic voltage scaling (DVS): In this subset of DVFS, selected portions of the device are dynamically set to run at different voltages on the fly while the chip is running.

Dynamic voltage and frequency scaling (DVFS): Selected portions of the device are dynamically set to run at different voltages and frequencies on the fly while the chip is running. Used for dynamic power reduction.

Adaptive voltage and frequency scaling (AVFS): In this variation of DVFS, a wider variety of voltages are set dynamically, based on adaptive feedback from a control loop; involves analog circuitry.

Power shut-off (PSO) [or power gating]: When not in use, selected functional blocks are individually powered down.

Memory splitting: If the software and/or data are persistent in one portion of a memory but not in another, it may be appropriate to split that block of memory into two or more portions. One can then selectively power down those portions that aren’t in use.

Page contents originally provided by Cadence Design Systems


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