The RTL simulation process involves a number of stages: evaluation, scheduling and time wheel management and fan-out tracing. Simulation accelerators incorporated special purpose hardware to assist with each of these functions and in some cases enabled them to be performed concurrently. Most of these were developed in the late 80s. Unfortunately, these only provided a very limited amount of speedup and the associated costs made it an unviable technology, especially since the speed of general purpose computers was increasing so rapidly during this period.
Other attempts were made to employ parallel computing to the task. In general ,the circuit was partitioned and each part simulated on a separate machine. However, communications and synchronization between the circuit parts meant that most designs would top out at being able to use a handful of processors effectively before communications costs caused the whole process to slow down. Most designs did not even show any significant speedup.
With the advent of processor based designs, some success was met with systems that used a physical backplane that corresponded with the bus in the design. This way communications costs were minimized and each IP block was assigned to a separate card in the accelerator. Still, companies such as Simutech, were unable to meet with any financial success.
The most modern form of this are attempts to use Graphics Processor Units (GPU) as simulation accelerators. These have very high speed communication paths between each of the processing units and in most cases do not require any special purpose hardware that cannot be found in a general purpose desktop computer.