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Software-Driven Verification

Verification methodology utilizing embedded processors
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Description

Hardware verification has traditionally used approaches that inject stimulus into a design and match the outputs of the design-under-test (DUT) with expected results. Initially, the stimulus and the expected results were created manually, but this was replaced by constrained random test-pattern generation which could automatically generate stimulus. Result checking was performed using a high-level model of the design. The methodology resulted in the creation of SystemVerilog and UVM. However, this methodology relied on the stimulus generator having full and predictive control over all of the inputs of the design. This became increasingly difficult when processors became an integral part of many sub-systems and SoCs. The methodology required that they be removed and replaced by bus-functional models.

Software-driven verification keeps the processors in the DUT and uses them as part of the verification methodology. Software is written to run on those processors to exercise the hardware. That software may either be created manually or generated automatically. In 2014, use cases were increasingly identified as the way in which verification scenarios were defined and from these tools create specific test cases, possibly using constrained random techniques. Commercial tools capture those use cases using graph-based methods although no standardization yet exists.

Another popular aspect of software-driven verification is that models of the processor can exist at multiple levels of abstraction and historically all of those models have been register accurate and object code compatible. This means that software compiled to run on the real processor, can also run on an instruction-set accurate model, or an abstract model, or one mapped into an emulator. This creates the ability to have test portability throughout the entire development cycle from virtual prototype, simulation, emulation, FPGA prototype and actual silicon.

In 2014, an Accellera group was formed to look at the standardization of portable stimulus that may bring about some degree of commonality into the way in which the use cases are defined.


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