Today’s single-exposure, 193nm wavelength lithography reached its physical limit at 40nm half-pitch. 193nm immersion lithography, coupled with multiple patterning techniques, enables chipmakers to image IC designs at 20nm and below.
One multiple patterning technique is called triple patterning. Using today’s 193nm immersion lithography, triple patterning may be required for 10nm and beyond. This technology is similar to double patterning. Double patterning refers to the litho-etch-litho-etch (LELE) pitch-splitting process in the fab, according to Mentor Graphics.
In comparison, triple patterning refers to the litho-etch-litho-etch-litho-etch (LELELE) pitch-splitting process. In the fab, LELELE requires three separate lithography and etch steps to define a single layer. LELELE provides a reduction in pitch. But LELELE can be expensive, as it triples the process steps in the lithography flow.
Simple patterns, including those in flash memory or the fins in finFETs, are done in self-aligned double patterning (SADP) or another version of the technology, self-aligned quadruple patterning (SAQP). In both techniques, lone parallel lines are formed, followed by cuts.
Metal levels in DRAM and logic chips are more complex and can’t be done with SADP or SAQP. These metal layers require LELE or LELELE. SADP and SAQP also have less design flexibility than LELE or LELELE. Hole-type patterns require LELE-type technology.
To enable advanced IC designs at 20nm and below, the manufacturing process imposes new layout, physical verification, and debugging requirements on the designer. These requirements can vary depending on the design methodology used and the particular foundry’s multi-patterning process.
On the design front, the challenge is trying to build an EDA software algorithm for automating the decomposition (coloring) and checking of a layer using triple patterning. Triple patterning violations can be quite complex, and debugging can be tricky, but the challenges are manageable with software that helps the designer understand the design issues.