Multi-supply voltage techniques operate different blocks at different voltages. Running at a lower voltage reduces power consumption, but at the expense of speed. Designers use different supply voltages for different parts of the chip based on their performance requirements. MSV implementation is key to reducing power since lowering the voltage has a squared effect on active power consumption.
MSV techniques require level shifters on signals that go from one voltage level to another. Without level shifters, signals that cross voltage levels will not be sampled correctly.
The synthesis tool’s optimization engine should automatically calculate the worst-case paths in the design. In addition, synthesis can support top-down multi-supply voltage synthesis, assigning different libraries to different voltage domains in the chip and performing top-down analysis and optimizations.
Multi-supply voltage techniques can reduce power consumption of SoCs that do not require all blocks to operate at maximum speeds at all times. Designers use different supply voltages for different blocks of the chip based on their performance requirements. MSV implementation is key in reducing power, since lowering the voltage has a squared effect on active power consumption.
Top-down MSV synthesis features include the following:
• Multiple voltage domains
• Assign libraries to domains
• Assign blocks to domains
• Top-down analysis and optimization
• Level shifter insertion
Synthesis uses the power domain concept to describe switchable blocks with different supply voltages. Level shifters are added to ensure that blocks operating at different voltages will operate correctly when integrated together in the SoC. Level shifters must ensure the proper drive strength and accurate timing as signals transition from one voltage level to another. A power domain is a collection of design blocks or instances that share the same supply voltage.
In the diagram, three power domains are shown (A,B and C). Each voltage domain has a separate library associated with it.
For placement and optimization in a top-down situation where the design is being implemented as a whole, a tool needs to understand that power domain boundaries must be honored. That is, the tool knows that no logic from one power domain can be moved to another power domain.
In addition, during placement and optimization, the tool should be able to use the correct timing libraries set for each of the power domains. For example, when the tool is optimizing the 0.8V power domain, it should use the timing libraries characterized at 0.8V.
Theoretically, since power is proportional to voltage squared, by lowering the voltage we should get an exponential decrease in power consumption. In reality, this is not necessarily so, because in the physical world, lower voltage means timing issues and increased transition time, which translates into more power consumption.
To fix timing issues, logic needs to be upsized or inserted, also resulting in more power consumption. Overall, operating at a lower voltage definitely gives power savings, although not as much as theoretically would be possible without reference to timing issues.
On a sample of designs, multi-supply voltage optimization reduced dynamic power by 40-50% and provided a 2X improvement in leakage power. The addition of level shifters add up to a 10% area overhead and may impact clock scheduling. Added design complexity may increase design turn-around time.
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