The cell-aware test methodology is well suited for addressing defect mechanisms specific to FinFETs. Consider a FinFET transistor with three fins. Research suggests that two defect types should be considered for such transistors: leakage defects that force the transistor partially or completely on, and drive-strength defects that force the transistor partially or completely off.
The leakage defects can be analyzed by placing a resistor across the gates (from drain to source) of each of the transistor’s three fins as shown below. During the cell-aware characterization process, analog simulation is performed with varying resistive values for all resistors for all FinFETs in a given library cell. Exhaustive analog simulation must be performed for both single-cycle and dual-cycle tests, as many of these resistive defects will only result in small extra delays to the transistor’s response and the output of the cell.
The drive-strength defects can be analyzed by placing a resistor between the drain and each of the fin’s gates and between the source and the fin’s gates as shown below. As with leakage defects, analog simulation is performed with varying resistive values for each of the resistors. Once again, both single and dual cycle tests must be simulated to detect delay-related effects.
Any additional defect types that are discovered and are relevant to FinFETs can be handled in a similar fashion. The generic approach to analog defect simulation used by the cell-aware methodology makes this straightforward.
Once the cell library characterization is completed, the result is a UDFM model that can be used with the ATPG tool. After reading the UDFM file, the ATPG cell-aware pattern creation process proceeds similar to any of the other fault models.
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