Known alternately as margin or margining, guard-banding is a way of making sure that if one part of a design fails, the chip still can continue to operate.
Guard banding is standard operating procedure in designs at 65nm and above, but as power and performance have become much more entangled with process geometries, adding extra circuitry has cost both performance and power. After 20nm, many design houses believe that guard-banding sharply eroded the benefit of moving to the next process geometry. The reason has to do with a combination of extra wiring, which can lengthen the signal path and slow the operation of a chip, and the thinness of the wires themselves, which result in RC delay and generate heat. In designs with finFETs, extra circuitry also can contribute to an increase in dynamic power.
At the most advanced nodes, the big push is toward correct-by-construction, meaning the design needs to be much more exact with fewer respins.