Back in the 1970s, a company by the name of Calma created a workstation out of a general purpose computer and a graphics display. This was used to create layout data for the emerging field of integrated circuit design. Back then, there was no Ethernet, in fact very few ways in which computers could talk to each other. The most common way was using magnetic tape. Calma needed a way to transfer the graphics database between machines. A second generation of machines came with an updated binary transfer format that they called Graphics Database System stream format II or GDS II. That standard is still in use 40 years later and only in 2001 did efforts start to define a possible replacement format - OASIS.
Standards enable compatibility between tools and flows and can eliminate wasted time and effort when every tool vendor has to define the same types of capability. In the early 80’s, when the EDA industry was emerging, it didn’t care about compatibility issues. In addition, many of the core capabilities required (databases, graphics systems etc.) were not supported by suitable standards. Each vendor was quite happy to lock users into their flow and they designed closed databases for everything. That not only made their systems sticky, but also stopped smaller startups from piggy-backing on their infrastructure.
Users pushed back because they wanted to put together design flows that were composed of the best tools in each category rather than accepting integrated mediocrity. In 1983 work started on the Electronic Design Interchange Format (EDIF), a neutral format that would enable data to be moved between the proprietary databases. Each vendor wrote translators to and from their internal database and this neutral format. Even though EDIF 1.0 was published in 1985 it took another three years before EDIF 2.0 was released and was usable enough to accomplish the original goal. It also became an ANSI/EIA standard.
In 1984, a company called Gateway Design Automation came up with a new language called Verilog. That language evolved over time and it was licensed by an emerging synthesis company called Synopsys. Cadence acquired Gateway in 1990 and continued to develop the language and the simulator that went along with it.
Around the same time, a US Government program devised the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (HDL), or more commonly referred to as VHDL, based on the ADA language that had been defined for software. In 1987, this language became IEEE standard 1076. There were some holes in the original VHDL standard such as the lack of any usable data types for representing logic. Groups formed to solve these issues and tools started emerging based on this standard.
Cadence became scared that if they did not make Verilog an open standard, the industry would shift to VHDL and the powerful combination of Cadence and Synopsys would be lost. So in 1990, Cadence formed Open Verilog International (OVI) and in 1991 transferred the documents for the Verilog language to OVI for continued development. OVI both improved and attempted to make the language as vendor neutral as possible. In 1994 it was turned over to the IEEE and a more formal standardization process, emerging as IEEE 1364.
The industry now had two languages. These were not exchange languages as had been the case with EDIF, but the source languages that could be used to drive all of the other tools in the flow. This helped to stimulate innovation within the industry and better tools emerged. It also enabled smaller EDA companies to play alongside their bigger cousins. However, the existence of two competing languages has been described as the most costly mistake of the EDA industry.
The EDA industry has grown a lot since those years and today we have organizations creating a myriad of standards. There is debate within the industry as to the best time to create a standard. Standardization provides interoperability, an important factor in adoption. However, there is also the thought that standards stop or slow down innovation.