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Simon Davidmann
Serial entrepreneur and technologist
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Description:

Davidmann is a serial technologist and entrepreneur who has helped several companies establish themselves in Europe (Gateway Design Automation, Chronologic Simulation, Virtual Chips, Ambit) and then founded his own companies.

His passion for EDA started at the University of Essex and then later at Brunel University where he was one of the developers of the Hilo RTL simulation language and simulator. This was the foundational technology for Verilog.

His first was Co-Design Automation. The focus of the company was simulation solutions for design and verification and to develop the first ‘next generation’ Hardware Design and Verification Language (HDVL). Co-Design developed Superlog as which became a foundational technology for SystemVerilog. Co-Design was acquired by Synopsys, Inc. in Sept 2002.

In 2005, Davidmann founded Imperas, a company developing software tools to assist in the programming of multi-core embedded processors and systems. After a change in direction, Imperas concentrated on the modeling of systems and the creation of virtual prototypes for software development and debug. They established Open Virtual Platforms for the modeling side of the business and concentrated on developing tools for simulation and debug technologies for software.



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