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IEEE 1850

Verification language based on formal specification of behavior


PSL is a formal notation for specification of electronic system behavior, compatible with multiple electronic system design languages, including IEEE Std 1076 (VHDL), IEEE Std 1354 (Verilog), IEEE Std 1666 (SystemC), and IEEE Std 1800 (SystemVerilog), thereby enabling a common specification and verification flow for multi-language and mixed-language designs.

PSL captures design intent in a form suitable for simulation, formal verification, formal analysis, and hybrid verification tools. PSL enhances communication among architects, designers, and verification engineers to increase productivity throughout the design and verification process. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.

A Practical Introduction to PSL (Integrated Circuits and Systems)

  • Other names: PSL, Property Specifciation Language
  • Type: EDA



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