Boundry Scan Test
The Joint Test Action Group (JTAG) formed in Europe in the late 1980s. Up until that time, most printed circuit boards (PCBs) were populated with chips that had exposed pins that were soldered through the board. Because of increasing board densities and increased integration within the chips, chip packaging migrated to a surface mount type of assembly, meaning that the contact points became hidden under the chip. Unless important points were exposed elsewhere on the board, taking space and adding to complexity, it became impossible to connect probes to them. This had a serious impact on the ability to test the board.
Boundary scan was the solution they came up with. It dedicated a few pins on the chip, called the JTAG port, that was used to access an internal scan chain. A scan chain enables the value of many of the state storage elements in a chip to have their value either set or read. In this way, the values on the external pins of the device could be set in one chip and the values checked in other chips on the board that they were meant to be connected to. In this manner, open circuits, short circuits and other fault types could be easily detected.
The standard port consists of either 4 or 5 pins: TCK (test clock), TMS (test mode select), TDI (serial test data input) and TDO (serial test data output) plus an optional TRST (test reset). Along with the port, a standard controller is defined that enables a minimum set of functions to be performed, such as scanning data in or out.
IEEE 1149.1 Boundary-Scan Standard and the associated Test Access Port (TAP) were first released in 1990.
While the initial use case was for structural testing of PCBs, it has since been extended and adapted for many additional functions, including internal chip testing, FPGA programming, software reprogramming and more others.
Boundary Scan Description Language (BSDL) is a modeling language for boundary scan devices based on a subset of VHDL. It became part of the 1149.1 standard in 2001. It enables users to provide a description of the way in which boundary scan was implemented so that test generation tools can correctly access the device and the capabilities built into it.
The Boundary - Scan Handbook
IEEE 1149.1:IEEE Standard Test Access Port and Boundary Scan Architecture
IEEE 1149.2 Extended Digital Serial Interface
– Attempted to develop a standard that supported boundary scan for board-level interconnect testing and supported internal scan for device- or board-level component testing. The group's overall objective was to establish minimal mandatory features that are adaptable to individual applications. It never became a standard.
IEEE 1149.3 Direct Access Testability Interface
– Never became a standard and much of its work was consumed by IEEE 1149.5.
IEEE 1149.4 Standard for mixed-signal test
While IEEE 1149.1 can test the digital portions of a design, including the transfer of signals between the analog and digital domains, it cannot handle any of the true analog aspects of a design.
IEEE 1149.4 was first released in 1999 and provided serial analog access to all analog pins of a device and a standard 2 pin analog TAP design to operate effectively for frequencies below 100kHz.
Analog and Mixed-Signal Boundary-Scan: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing)
Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing)
IEEE 1149.5 Standard Module Test and Maintenance (MTM) Bus Protocol
and is a derivative of the VHSIC TMbus.
This standard specified a serial, backplane, test and maintenance bus (MTM-Bus) that was used to integrate modules from different vendors into testable and maintainable subsystems. Physical, link, and command layers were specified. Standard interface protocol and commands could be used to provide the basic test and maintenance features needed for a module as well as access to on-module assets (memory, peripherals, etc.) and IEEE Std 1149.1 boundary-scan. The standard has been withdrawn.
IEEE 1149.6 Boundary-Scan Standard for Advanced Digital Networks
1149.6 was added in 2003 to address the increasing utilization of high-speed, AC-coupled or differential serial buses, commonly known as SerDes (serial/deserializer). Examples include Gigabit Ethernet, Fibre Channel, PCI Express, USB and others. The extension is often called AC-EXTEST.
Compliant devices use the transmitting and received ends of a connection to send and receive pulses of data.
IEEE 1149.6-2003: IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks
IEEE 1149.7 Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan Architecture
This standard optionally reduces the JTAG port to only two device pins and adds certain functionality to the IEEE 1149.1 base standard while still providing access to the IEEE 1149.1 TAP. It can support multiple embedded TAP controller architectures. IEEE 1149.7 extends the test and debug capabilities of the TAP to complex devices like systems-on-a-chip (SoC), system-in-package (SIP) and other multi-core or multi-die devices. It became a standard in 2009. It is sometimes referred to as compact JTAG or cJTAG
IEEE 1149.7-2009: IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture
IEEE 1149.8.1 standard for testing interconnects to passive/active components
Standardizes the boundary-scan structures and methods required to extend boundary-scan testing of connections to passive and/or active components. The use of selective or differential signals which when combined with noncontact signal sensing or a vectorless sensor plate, will allow testing of the connections between devices that adhere to this standard and circuitry elements such as series components, sockets, connectors and semiconductor devices that do not implement IEEE 1149.1 standards. The standard was released in 2012.
The Boundary - Scan Handbook
- Other names: JTAG
- Type: Design