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Verilog-AMS

Analog extensions to Verilog
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Description:

Verilog-AMS is an analog mixed-signal version of the Verilog standard. It was standardized under Open Verilog International (OVI). The first stage of development was Verilog-A, the set of continuous-time constructs necessary to describe analog circuitry. This was based on the Spectre language. Verilog-A was not intended to work directly with Verilog-HDL. Rather it was a language with similar syntax and related semantics that was intended to model analog systems and be compatible with SPICE-class circuit simulation engines.

Verilog-A was standardized by OVI in 1996, and Verilog-AMS 1.3 was release in 1998. Version 2.0 was completed in 2000 and all further work was conducted within Accellera. The last version of Verilog-AMS was 2.4 and released in 2014 and is based on IEEE 1364-2005. This will be the last version of it because since that time, Verilog has been replaced by SystemVerilog. The analog extensions have never been turned over to the IEEE.

The working group is currently working on alignment of Verilog-AMS with the SystemVerilog work of the IEEE 1800, or inclusion of AMS capabilities in a new "SystemVerilog-AMS" standard. In addition, work is underway to focus on new features and enhancements requested by the community to improve mixed-signal design and verification, as well as to extend SystemVerilog Assertions to Analog and Mixed-Signal designs through the subcommittees.

  • Type: EDA

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