Hardware Description Language
VHDL was an offshoot of the VHSIC (Very High-Speed IC) program, funded by the U.S. Department of Defense (DoD), and was ﬁrst proposed in 1981. Language development was done by Intermetrics Inc, who were language experts, Texas Instruments as chip design experts and IBM as system design experts. The language was based on Ada, an earlier DoD language developed for software.
At the end of the program, in March of 1986, the role of standardizing the language was given to the IEEE who formed the VHDL Analysis and Standardization Group (VASG). It became an IEEE standard in 1987 – IEEE 1076. At that time, military contracts required that VHDL descriptions were delivered for all ASIC designs.
In 1991, VHDL International (VI) was formed. Its charter was to promote the existing standard and to work on possible extensions to the language in co-operation with the IEEE. VI later merged with OVI to form Accellera. Accellera has continue to act as the body that develops new capabilities for the language that are then transferred to the IEEE for further refinement and ratification.
While VHDL included a wide range of data types, it lacked the ability to represent multi-valued logic, so an additional standard was created to define std_logic and its vector equivalent. This was a 9-value logic system and became IEEE 1164.
VHDL went through IEEE updates in 1993, 2000, 2002, 2008 and Accellera updates in 2006 and 2008
For a short period of time 1076a also existed based on the 1993 version that included shared variables with a well-defined concurrency control mechanism. This was merged back into the 2000 version of the standard.
While Verilog has become the preferred language for ASIC design, VHDL remains the dominant language for FPGA development.
The high-level structure of a VHDL model may contain the following building blocks:
Entity – the most basic building block, represents the external view of a device.
Architecture represents the internal view of the device, its behaviour and structure.
Configuration binds a component instance to an entity/architecture pair.
Package – a grouping of commonly used elements.
Bus is a signal that can have its drivers turned off.
Driver is the source of a signal
Attribute – data attached to a VHDL object or predefined data about VHDL objects
Generic a parameter that passes into an entity.
Process a unit of execution.
The Designer's Guide to VHDL, Third Edition (Systems on Silicon)
Circuit Design and Simulation with VHDL
FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version
Digital Electronics: A Practical Approach with VHDL (9th Edition)
- Other names: VHSIC HDL, IEEE 1076
- Type: EDA