Manufacturing Bits: Dec. 29

Printing hair; 2D material FETs; black phosphorus chips.


Printing hair
Using a low-cost, 3D printing technique, Carnegie Mellon University has found a way to produce hair-like strands and fibers.

The printer produces plastic hair strand by strand. It takes about 20-25 minutes to generate hair on 10 square millimeters. A video can be seen here.

A miracle cure for hair loss? (Photo: Carnegie Mellon)

3D printed hair (Photo: Carnegie Mellon)

The hair can be made using a fused deposition modeling (FDM) printer. In the process, a plastic filament passes through a heated nozzle. The nozzle produces strings of molten material into patterns. FDM printers are inexpensive and cost about $300.

2D material FETs
Transition metal dichalcogenide (TMD) technology is a class of 2D materials that are gaining steam in the R&D labs.

The TMDs have remarkable electronic, optical and mechanical properties. One TMD, molybdenum disulfide (MoS2), is getting perhaps the most attention. In the lab, several universities and research organizations are developing futuristic devices called MoS2 FETs.

At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., École Polytechnique Fédérale de Lausanne (EPFL) and the Indian Institute of Technology (IIT) put a new spin on the technology. Researchers devised MoS2 RF transistors with gate lengths at 70nm and 40nm. The technology could be used for futuristic 2D semiconductors on flexible and rigid substrates.

“We (reached) a cutoff frequency for voltage gain of 50 GHz in the case of trilayer MoS2 FET with a 70nm gate length,” according to the paper at IEDM. “In order to decrease the contact resistance and to improve the properties of our devices in RF range, we introduced the ‘edge–contacted’ injection in trilayer MoS2 RF-FETs. With this approach we boost the performance of our devices to the values of fT = 25 GHz, fMAX = 16 GHz and Av = 45 GHz for trilayer MoS2.”

To make the MoS2 RF devices, MoS2 materials were exfoliated onto a silicon substrate. Then, contacts were patterned using electron-beam lithography. Following that step, 70nm thick gold electrodes were deposited. “This was followed by an annealing step at 200 °C in order to remove resist residue and decrease the contact resistance,” according to the paper.

“Atomic layer deposition (ALD) was used to deposit a 20nm thick layer of HfO2 as (a) high-κ gate dielectric. Local top gates for controlling the current in the two branches were fabricated using another e-beam lithography step followed by evaporation of 10nm/50nm of Cr/Au,” according to the paper. “In order to enhance carrier injection, in some devices we also pattern MoS2 in the contact area by introducing cuts, with the aim of increasing the total length of the MoS2 edge under the metal electrode.”

Black phosphorus chips
Another TMD, phosphorene or black phosphorus (BP), is also a promising technology. This 2D material has a direct band-gap and high-electron mobility.

So far, however, BP devices simulated have been restricted to double-gated structures. “Furthermore, due to the weak van der Waal (vdW) forces in the BP layers, the electrostatic potential at individual layers for thicker BP could be different in (a) single top gate device which may adversely affect the leakage current,” according to a recent paper from the National University of Singapore and Northeastern University.

In fact, the National University of Singapore and Northeastern University may have discovered a new breakthrough in the arena. Researchers devised a few-layer BP FET with a 7nm channel. They investigated the device performance of a few-layer BP FET based on two structures–a single-top-gate device structure MOSFET and a Schottky barrier (SB).

“Our results showed that the performance of single-top-gate monolayer BP MOSFET has the best performance, and it degraded as the layer number increased with a reduced ON-current (ION) and increased sub-threshold slope (SS), due to the weak interlayer interaction resulting in the inefficient gate control of the BP layers away from the gate,” according to the paper, which was presented at IEDM.

“In addition, the SB FETs showed comparable performance between different BP thicknesses as the SB is more effective in reducing the OFF-state current. Lastly, acoustic phonon scattering was included for monolayer BP MOSFET, indicating a 42% reduction in ION due to back scattering of carriers for 7nm channel FETs,” according to the paper.