Measuring FinFETs Will Get Harder

No one tool does everything, and the best tools for the job are slow.

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The industry is gradually migrating toward chips based on finFET transistors at 16nm/14nm and beyond, but manufacturing those finFETs is proving to be a daunting challenge in the fab.

Patterning is the most difficult process for finFETs. But another process, metrology, is fast becoming one of the biggest challenges for the next-generation transistor technology. In fact, metrology is becoming more complex and expensive at each node.

It’s a relatively straightforward process to characterize today’s planar devices. It takes just a handful of metrology tool technologies to do the job. It’s a different story with finFETs, however. Unlike planar transistors, which are two-dimensional devices, finFETs are three-dimensional structures that are difficult to measure. In some cases, the structures are well below an angstrom and are complex at every turn. (An angstrom is equal to 0.1nm.)

At last count, metrologists are using nearly a dozen different metrology tool types to characterize today’s finFETs. That includes traditional tools as well as nearly a half-dozen different X-ray metrology systems. And metrology won’t get any easier at 10nm and beyond.

“Metrology is becoming a huge challenge,” said Isaac Mazor, vice president and general manager of the X-ray semiconductor business at Bruker. “The number of parameters is growing. Customers will need to use all tools in a mix-and-match (mode). But as we move to 28nm and below, and down to 10nm and 7nm, we will see a substantial increase in X-ray metrology.”

Indeed, metrologists face several challenges. First, they must select the right tools on a limited budget. Second, the selection process is becoming increasingly difficult. In X-ray metrology, for example, there are a dizzying array of technologies with the following acronyms—CD-SAXS, HRXRD, LEXES, TXRF, XRD, XRF, XPS and XRR.

And finally, the metrology vendor base is consolidating, leaving chipmakers with fewer choices in the market. Generally, the smaller metrology vendors lack the resources to advance their product roadmaps. And so, the larger vendors are gobbling up the smaller firms to expand their portfolios.

Merger mania hit the metrology world earlier this year, when Nova acquired ReVera, a supplier of X-ray photoelectron spectroscopy (XPS) tools. And recently, Bruker acquired X-ray metrology tool specialist Jordan Valley Semiconductors. (Prior to the acquisition, Bruker’s Mazor was the chief executive of Jordan Valley.)

The big blockbuster occurred in October, when Lam Research entered into a definitive agreement to acquire process-control tool giant KLA-Tencor for $10.6 billion. With the proposed move, Lam will enter into the inspection and metrology market.

There are other motives behind the proposed deal. “The other aspect is that as you shrink below 10nm, the process control aspect of it is becoming more important,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “Now that we are controlling things on the atomic level, very small variations can impact the end result. It’s not just from a defect yield perspective, but also from a device performance perspective. That was one of the big keys that led us to realize we have to get much closer in the process control space.”

The metrology challenges
To be sure, the metrology world is in flux. Today, chipmakers use the traditional metrology tools to characterize planar devices. Those tools include atomic force microscopy (AFM), the critical-dimension scanning electron microscope (CD-SEM), and optical CD (OCD).

AFMs use a tiny probe to enable measurements. CD-SEMs take top-down measurements. And one OCD, called scatterometry, measures the changes in the intensity of light.

These tools work for planar devices, but finFETs present another set of challenges. For example, planar devices require six different CD measurements. In comparison, finFETs require 12 or more different CD measurements, such as the gate height, fin height and sidewall angle.

And that’s just the tip of the iceberg. “Process windows for finFET formation as well as cut masks shrink quickly as multiple litho, etch and deposition steps contribute to final pattern variability,” said Ady Levy, vice president of the Patterning 5D and Marketing Divisions at KLA-Tencor. “In addition, increased measurement sampling is needed to capture the cross wafer variation as well as time variability, driving the need for fast metrology measurement techniques that can be implemented in production.

“At the advanced nodes, finFETs also require tight film deposition control around the gate stack,” Levy said. “Since the quality of these films directly correlate with transistor electrical performance, a new generation of film measurement tools is needed with the capability to measure and provide feedback on these critical film layers with significantly tighter accuracy and precision.”

The problem? AFMs, CD-SEMs and OCD can make three-dimensional measurements for finFETs, but they each have various limitations. For example, the CD-SEM provides some but not all three-dimensional imaging capabilities. The AFM is slow in terms of throughputs.

OCD requires complex and time-consuming models. It also requires reference data to calibrate the tool. One way to obtain reference data is to cut the wafer and examine the cross section using a transmission electron microscope (TEM). But at times, this is a slow and an expensive process.

The solutions
So what’s the solution? Unfortunately, there is no one tool that can handle all metrology needs for finFETs. So chipmakers are throwing a number of tool technologies at the problem. For example, today’s atomic layer deposition (ALD) is used in several applications, such as the formation of capacitors for DRAM, the gate-stack in logic, multi-patterning and others. “ALD-enabled patterning will need to be characterized,” said Han Jin Lim, a technical staff member at Samsung’s R&D Center. “Current metrology has been evolving, and thus (the industry) is using CD-SEM, OCD and others.”

But fortunately, vendors are improving the capabilities of their tools, thereby giving metrologists a fighting chance.

Today, OCD is the workhorse technology in the in-line metrology flow for finFETs. OCD characterizes and monitors the fin shapes and CDs. “As a result of the improved capabilities of the latest-generation optical CD systems, the industry is transitioning to this technology for patterning control at 10nm,” KLA-Tencor’s Levy said. “But as the industry moves from one design node to the next, the challenges for metrology tools, whether optical or electron-beam, have always included signal-to-noise ratios, accuracy, matching ease-of-use and production worthiness. Another challenge is reducing reliance on complex geometric models for optical CD measurements and taking the step toward enabling direct correlation of optical CD measurements to parameters, such as focus, dose and CD. This, in turn, can drive faster-time-to-result and better patterning control.”

OCD is being used for some but not all finFET applications. “OCD is doing the fins well,” said Ofer Adan, global product manager at Applied Materials, a supplier of CD-SEMs and other products. “But in regard to gate over the fin, [OCD] is not doing very well. It is taking too long in development. It is also losing the correlations between in-die and scribe.”

For gate over fin applications, the CD-SEM is making inroads in the flow, Adan said. To enable this application, Applied Materials added tilt-beam technology to its CD-SEM, which can image structures from an angle.

Another technology, AFM, is also making inroads, as vendors have improved the ease-of-use for the tools. Samsung, for one, used AFM to evaluate SRAM cells within a NMOS part of a finFET structure at 10nm. “(An) AFM-based nano-probing system has no electron-beam damage, because it uses topography images created by AFM instead of SEM for guidance at (the) contact level,” said Jonghyuk Kang, an engineer at Samsung, at a recent event.

Still, the traditional tools aren’t quite enough. To illustrate the problems, GlobalFoundries recently presented a paper on the metrology challenges for a hypothetical SOI finFET. The goal was to characterize the CDs, thickness and the composition of a silicon-germanium (SiGe) compound in the fin.

GlobalFoundries evaluated both OCD and X-ray metrology tools. “Scatterometry is something that can measure fins. However, we do require reference metrology to validate it. And it typically works over a tight process window,” said Kriti Kohli, an advisory engineer at GlobalFoundries.

Hoping to find an alternative solution, GlobalFoundries evaluated various X-ray techniques, namely high-resolution X-ray diffraction (XRXRD), X-ray fluorescence (XRF), and a combination tool based on XPS and XRF. “Our goal was to evaluate multiple X-ray techniques and try to identify one that’s compatible as a high-volume manufacturing solution,” Kohli said.

XRXRD, or XRD, is used to characterize crystalline materials. XRF looks at surface contamination. And the XRF/XPS combo tool not only looks at the surface, but it is used to determine the composition and chemistry on a wafer.

Based on the results from the study, GlobalFoundries determined that the XRF/XPS combo tool is production worthy. XRXRD shows promise, but XRF was ruled out of the equation, according to the company.

All told, GlobalFoundries and other chipmakers will continue to use the traditional metrology techniques in production, but X-ray is making inroads. There are some trade-offs, however. “For high-volume manufacturing, scatterometry is the main option. It’s so much faster than the X-ray techniques. However, scatterometry does require reference metrology,” GlobalFoundries’ Kohli said.

Still, some X-ray metrology technologies are making vast improvements in terms of capabilities and throughputs. Others are stuck in R&D.

X-ray metrology is not new. A decade ago, chipmakers began to use X-ray reflectivity (XRR) for thin-film measurements. Over time, X-ray metrology has seen wider use, especially as chipmakers require more and difficult measurements at the Angstrom level. “Now, we are seeing (X-ray metrology used) even more in strained-silicon with silicon-germanium,” said Adam Feinstein, director of product management at Bruker, a supplier of AFMs, X-ray tools and other systems. “We are seeing it with raised source/drain at 14nm and 10nm. We will likely see it with III-V or SiGe fins as we go to 7nm and 5nm.”

Chipmakers are using several X-ray techniques, particularly XPS, XRD and XRF. “XRD is becoming a critical metrology technique for the selective growth of epi,” Bruker’s Mazor said.

The drawback for XRD is throughput. “XRF and XRR are not an issue in terms of productivity,” Mazor said. “XRD will require one more order of magnitude in terms of powerful sources.”

Meanwhile, the next big thing is a non-destructive technology called CD small-angle X-ray scattering (CD-SAXS). CD-SAXS boasts impressive resolutions, but the throughputs are slow. It uses an X-ray source that currently doesn’t generate enough power.

CD-SAXS is making progress, at least in R&D. In the lab, Intel and the National Institute of Standards and Technology (NIST) patterned 12nm lines on a device. The spaces between the lines were less than 0.5nm. Using CD-SAXS, researchers obtained measurements that were accurate down to 0.1nm.

CD-SAXS isn’t ready for prime time, however. “Throughput is still the primary limitation,” said Joseph Kline, a materials engineer at NIST. “There are several companies and research groups working on new compact X-ray sources that would make CD-SAXS viable if the sources work as proposed.”



  • Mark J. Hagmann

    You stated that “metrology is fast becoming one of the biggest challenges” and “more complex and expensive at each node”. I want to specifically address dopant and carrier profiling which are related to what you have done and how it will work. The roadmaps used to recommend that the resolution for profiling be finer than the 10% of the lithography node. Atom probe tomography may be adequate for dopant profiling, but do you believe new technology is required for carrier profiling below the 10 nm node? SSRM claims a resolution of 2 nm but changes the lattice out to a radius of about 10 nm. What would you recommend to go beyond SSRM? Is this topic is receiving sufficient attention?
    Mark Hagmann, NewPath Research L.L.C.

  • Mark LaPedus

    Hi Mark. Tell us more about atom probe tomography. What are the benefits? It is a lab tool or fab tool?