Memory Model Verification at the Trisection of Software, Hardware, and ISA (Princeton)

Princeton University researchers have discovered a series of errors in the RISC-V instruction specification

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Source: Princeton University, Caroline Trippel, Yatin A. Manerkar, Daniel Lustig*, Michael Pellauer*, Margaret Martonosi
*NVIDIA

Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for analyzing computer memory use, the team found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. The researchers warned that, if uncorrected, the problems could cause errors in software running on RISC-V chips. According to the researchers, officials at the RISC-V Foundation said the errors would not affect most versions of RISC-V but would have caused problems for higher-performance systems.

For technical paper, click here.
For Princeton’s news article, click here