Micro-Architectural Exploration for Low Power Design

In the first part of this series, we had discussed the need to perform power optimizations and exploration at higher levels of abstractions where the potential to reduce the power consumption is highest. We presented the need for making coarser changes at higher level of abstractions to exploit full power saving potential. In the second part, we discussed some very potent micro-architectural techniques for saving power: shift register to circular buffer transformation, flop cloning and memory banking. We had concluded the second part with the question: So why is not every designer deploying such micro-architectural techniques to save power?

The simple answer is that when it comes to power exploration, designers are mostly flying blind. There is no easy way of knowing whether there is even scope of saving power for a given design. Blindly applying every available technique, in the hope that power would be eventually saved, could ultimately end up hurting power. Designers need precise information about which of the available techniques will provide exactly how much power saving for their designs.

Traditionally, power estimation of the design has been used extensively to find power hot-spots. These hot-spots then, hopefully, lead to finding a sub-optimality, which can be fixed by design change. Most accurate power estimates are available only post-layout, but that being a very time-consuming process, designers tend to rely more on RTL power analysis to get an early assessment of power hungry regions of a design. Even though power analysis is an important step in power exploration, this itself is not sufficient since:

1. It provides a number, it does not identify wasted power.
2. It may require several team members to create an actionable plan to fix wasted power.
3. It requires multiple iterations to compare design changes.

Just the fact that design is consuming high power does not mean that power can be saved. Power can only be saved if it is being wasted (there is redundant activity which is not resulting in any meaningful output). The figure below gives an example of wasted activity:

Output of register “op_a” is fed into three different computations. However, only one computation is used depending on the value of register “instr”. So if the value of “instr” is “10”, the addition and multiplication operations are wasted. This is wasted power. Simple power analysis of this design would not reveal that there is wasteful activity occurring in the design. The designer’s problem is that there are too many choices but too little time to explore.

Let’s see what is it in the current power exploration flow that makes it very difficult for a designer to explore multiple design choices. The figure below shows a fairly commonly used power saving trick (block level clock-gating) being evaluated for its power saving potential.

First, the designer implements the change in RTL. Then the design change needs to be verified for correctness and the design is re-simulated to generate new vectors. Multiple iterations could be needed to optimize the design for this change. Then you take it through synthesis (for more accurate estimates) and do power estimation. More often than not, the team doing RTL design is different from team doing verification which in turn is different from team doing implementation and power measurement. So just to evaluate one design change, multiple tools, licenses and teams had to be involved. This whole process can easily run into days or weeks. Imagine repeating it for hundreds of design changes. This lengthy cycle of power exploration is single biggest deterrent for achieving maximum power savings for a design.

So the designer needs help on two fronts: 1) Precise knowledge of which power saving techniques will work for his design, and 2) A very quick way of estimating power saving for a design change. If these two are made available, that would hugely improve the turn-around time for power exploration.

Clock, memory and logic are the dominant consumers of design power. A designer would benefit from the knowledge of wastage happening on any component of power and which techniques would provide how much savings. For example, if there is redundant toggling on clocks, then which type of clock-gating (fine-grained, coarse-grained or block-level) would provide the best savings? A dash-board view of all power-savings potential would be the ideal place for a designer to start the power exploration.

In addition to what a tool can automatically find for power savings, a designer may want to try his own knowledge of the design to explore the power impact of a change. The current estimation flow (discussed earlier), requires a re-run of the changed design, and hence incurs the penalty of a full power estimation run on the entire design in addition to a rerun of simulation and synthesis on the entire design. In reality, most of design changes will impact small portions of the design. So to assess the impact of that change, redoing the complete design’s power estimation is an overkill. Because this process currently requires involvement of tools for simulation, synthesis and power estimation, as of now there is not much scope for incremental evaluation of power impact. An ideal exploration flow would provide for following:

• Allow the designer to make incremental change to the design.
• Figure out which portion of the design is impacted by this change.
• Re-simulate only the impacted portion.
• Re-synthesize only the impacted portion.
• Estimate power for only the impacted portion.

This requires assimilation of several disparate technologies (simulation, synthesis, estimation) under one single tool. The technique provides huge runtime benefits as it evaluates only the changed portion of the design and could provide very fast results and make it practical for the RTL designer.

We will conclude this series with a note that traditional ways of doing power exploration are no longer sufficient to maximize the power savings for a design. They discourage the designer from trying out multiple power saving choices. A new way of doing power exploration is needed that not only shows where power is being wasted in the design, but also provides a quick way of evaluating power impact of any design change (without the need for involving multiple tools or teams).