There are still problems to solve, but doing things the old way by shrinking every node may prove economically impractical.
The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit.
And now, there is another technology generating steam—monolithic 3D integrated circuits. In stacked-die, bare die are connected using TSVs. In contrast, monolithic integration involves a process of stacking, aligning and connecting leading-edge transistors on top of each other to form a so-called monolithic 3D chip. Using standard vias, monolithic 3D ICs are said to provide 10,000 times more connections at smaller feature sizes than stacked 2.5D/3D TSV technology.
This isn’t a new idea. Monolithic 3D integration was conceived several decades ago, but over the years, a number of entities have tried but failed to get the technology to work.
Now, the industry is beginning to address some of the challenges, making monolithic 3D chips a possible contender for the 7nm node and beyond. Today, in the lab, researchers have made some progress, claiming the ability to stack two layers of leading-edge transistors on each other. “I wouldn’t say it’s better (than 3D TSV technology), but monolithic 3D offers more versatility,” said Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. “You could have more connections between your two layers. And basically, the distance between the two contacts can be as short at 16nm.”
Given the current challenges with traditional IC scaling, IDMs, foundries and fabless chipmakers are taking a hard look at the technology. “The current buzz is going 3D,” said Aaron Thean, director of the logic program at Imec. “The next buzz is how to go 3D at the transistor level. There is more than one way to do that. We are currently evaluating those different ways.”
The big challenge for monolithic 3D is to process the top level without damaging the bottom layer. “The motivation is clear,” Thean said. “You are trying to increase device density. But when you try to bring this down to the transistor level, it’s tricky. It comes to a point that the stacking process itself can interfere with the processing of the transistor and the interconnect.”
For some time, 2.5D/3D technology has been gaining momentum. There are a couple of key reasons. First, the cost of traditional IC scaling is becoming astronomical. And second, the industry is beginning to see a bandwidth bottleneck in various chips.
“We’re coming to a point where raw scaling of circuits is probably not the best way to get the kind of productivity we need,” said Subramanian Iyer, a fellow at IBM’s Systems & Technology Group. “For example, by not scaling the die pitch and the board, we have put too much of the onus of the productivity gain on the semiconductor. This has increased the cost per function, which is not sustainable.”
To maintain the traditional IC scaling curve, the industry requires expensive technologies, such as extreme ultraviolet (EUV) lithography. An EUV scanner sells for $100 million to $150 million per tool. “It’s debatable that this industry can pay for those tools,” Iyer said. “No solution that I’ve seen today for lithography is actually sustainable. We can stay on Moore’s Law, but we need these orthogonal techniques to sustain it.”
Among those techniques is going vertical. In traditional DRAM scaling, for example, the industry “is struggling to keep pace,” said Mike Black, a technology strategist for Micron Technology. To help solve the problem, Micron recently began shipping the Hybrid Memory Cube (HMC), a 2GB device that is composed of a stack of four 4-Gbit DRAM die. HMC uses TSVs to combine the logic controller and the DRAM.
Another avenue is monolithic 3D integration, which was originally tried in the 1980s. “The industry encountered problems 30 years ago when we were depositing polysilicon,” said Albert Henning, chief scientist of MonolithIC 3D, an intellectual-property (IP) company that is developing monolithic 3D technology. “We had difficulties with the grain boundaries and the interfaces. That forced the industry not to use it as a means to make 3D transistors.”
More recently, monolithic 3D technology has been gaining steam. CEA-Leti, DARPA and universities have been working on the technology. Two IP vendors, BeSang and MonolithIC 3D, have been developing the technology.
Recently, SK Hynix licensed BeSang’s IP. In addition, Qualcomm is giving papers on the subject. And at the upcoming IEEE International Electron Devices Meeting (IEDM) in December, one group from Taiwan is expected to show one of the industry’s first monolithic 3D chips.
“Monolithic devices have been kicked around for a long time,” said Dean Freeman, an analyst at Gartner. “So, is this technology interesting? Yes. Is it practical? Tough to say. At this moment, it looks like it is pretty expensive, but so is 2.5D. Can it be cheaper than TSV or 3D alternatives? That’s too early to say. We will need to see them build an SoC and then compare it to a TSV or planar SoC.”
Needless to say, there are still some major challenges. “If you are building leading-edge devices with this technology, my concern is that you have thermal budget issues,” Freeman said. “You have to manage the thermal budgets of the different devices. You also have to manage the interconnects. If I am stacking transistors in close proximity, can I get the heat that I am generating out of the device? This is one of the challenges of any 3D technology.”
Today, there are several different types of fabrication flows for monolithic 3D integration. For example, in one flow from MonolithIC 3D, a chipmaker would first develop a conventional CMOS wafer, which would have transistors and copper interconnects. Then, the chipmaker would obtain a separate wafer or donor wafer. “We take a bare silicon wafer and oxidize it. We implant hydrogen, which means we implant protons. We implant them to about 20nm deep. The hydrogen layer creates a layer of damage in the single crystal silicon,” MonolithIC 3D’s Henning said.
Then, the donor wafer is flipped over and bonded on top of the original CMOS processed wafer using an oxide-to-oxide bonding process, according to MonolithIC 3D. At that point, the top of the structure is then cleaved or indented using either a mechanical force or annealing, according to the company.
Then, a chipmaker would form transistors on the top of the donor wafer, which is aligned and stacked on top of the bottom transistors. To form transistors on the top structure, a chipmaker would form so-called “recessed channel transistors” (RCATs) using etch and deposition tools. Then, the gate stack is formed, followed by the interconnects.
Another IP company, BeSang, has a somewhat similar flow. “BeSang’s 3D IC is also a monolithic 3D IC,” said Sang-Yun Lee, president and chief executive of the company. “It could be used for various applications without a specific limitation. It is not a specific product-oriented technology.”
Meanwhile, CEA-Leti, the current leader in monolithic 3D integration, is taking another approach using fully depleted SOI (FDSOI) technology. “Currently, we are developing the building blocks and the technology enablers,” said CEA-Leti’s Vinet. “We are working with the designers to identify the best suited applications for this technology. So we are just starting to identify the applications.”