Moore’s Law Reset?

Analysis: GlobalFoundries adds 22nm FD-SOI technology, extending benefits of planar design at least two more nodes with improved performance and lower power.


GlobalFoundries today took the wraps off its 22nm FD-SOI process, promising to extend Moore’s Law technologically without altering the economic equation—at least for the next couple of process nodes.

Subramani Kengeri, vice president of global design solutions at GlobalFoundries, said 22nm FD-SOI will provide the same 30% improvement in PPA that has been consistent with Moore’s Law scaling—a 50% reduction in area (cost) minus a 20% investment in new technology and equipment every two years. (See related video.)

While finFETs have offered a big improvement in performance, and a sharp reduction in leakage current due to better control of the gate using a three-dimensional structure, that progress has come at a price. More complexity in the design flow, from architecture to layout to more time-consuming verification resulting from higher dynamic power, plus double patterning with colors, all have added to the cost of developing a chip. In contrast, there are there are fewer masks to deal with using FD-SOI, and at 22nm (and even at 10nm, according to early testing) there is no need for finFETs because the insulation controls the leakage current. In fact, GlobalFoundries contends that controlling leakage is as good or better than finFETs at 16/14nm.

How this claim plays out in the real world remains to be seen, of course. Numerous sources interviewed on this subject say the key to making this work is getting the ecosystem up and running, which includes everything from IP to EDA tools, and executing the rollout plan. It also may depend, to some extent, on when EUV is fully functional and how competitively priced that technology will be. There are many question marks there, and timing is everything. The current plan for 22nm FD-SOI risk production is the second half of next year. EUV meanwhile is reportedly making progress, but it was supposed to be ready at 45nm.

Still, there are some strong arguments being made from the FD-SOI camp. For one thing, the operating voltage of 22nm FD-SOI is 0.4 volts, compared with 0.5 volts for finFETs, which should make it much more attractive for many applications. In addition, it says the operating voltage can be dropped as low as 0.3 volts in future releases. One added benefit of FD-SOI is that it allows chipmakers to use forward and reverse biasing, well-known techniques that ran out of steam at 40nm using bulk CMOS.

Moreover, developing chips at 22nm allows chipmakers to continue using single patterning for the middle end of line. While double patterning is still an option for metal one and two for increased density and bidirectional patterning, it is not a requirement. GlobalFoundries also claims that it has improved performance at 22nm to the point where it is competitive with finFETs, which was one of the reasons why some of the leading chipmakers opted to use finFETs in the first place.

GlobalFoundries now offers both 14nm finFETs and 22nm FDX, and it is working on 10nm version of both. It also has access to the technology developed by IBM at 7nm through its acquisition of IBM’s semiconductor division, which relies on EUV for some of the metal layers. IBM unveiled a 7nm test chip in conjunction with Samsung and GlobalFoundries last week based on a silicon germanium substrate.

The 22nm FD-SOI technology was developed over the past 2.5 years with the help of IBM, CEA-Leti, Soitec and STMicroelectronics. Kengeri said finFETs will continue to be a mainstay for some customers, particularly those developing server and high-end smartphone SoCs. But for the rest of the market—notably automotive and IoT and less costly mobile devices—the ability to achieve similar performance gains at extremely low power for a predictable ROI will be especially attractive.

According to GlobalFoundries, the new 22FDX process uses up to 20% less die size than 28nm, 10% fewer masks, and 50% fewer immersion lithography layers. The company plans to manufacture chips using this process at its 300mm production line in Dresden, Germany. There will four flavors: ultra low power for mainstream and low-cost smart phones; ultra high performance for networking applications with analog; ultra-low leakage for wearable IoT devices; and radio frequency analog for higher data rates.

While the details are just now being released, 22nm FD-SOI has been mentioned in several presentations over the last year (“Time To Look At SOI Again,” “Foundries Expand Planar Efforts,” and “One-On-One: Thomas Caulfield.”

The move also sheds some light on a number of projects that have been ongoing behind the scenes, just in case EUV failed to materialize. IBM has been at the forefront of that effort, working on FD-SOI finFETs and stacked die with through-silicon via, while Imec has tended to focus more on advanced finFET design and stacked die. Most chipmakers have intersected with one or both of those efforts, either through SUNY Albany with IBM, Samsung and GlobalFoundries, or Imec with all three plus many others, notably STMicroelectronics and CEA-Leti. IBM’s 7nm test chip, produced with the help of Samsung and GlobalFoundries is a case in point. Work in directed self-assembly has been ongoing just in case EUV didn’t ever show up, as well, and there has been more work underway in areas such as atomic level deposition and selective deposition. So while chipmakers have been in a panic over rising costs of design and manufacturing, others have been working furiously behind the scenes to smooth transitions down to the next few nodes.

That doesn’t mean that costs won’t continue to rise, or that Moore’s Law has a clear path ahead, but it does mean that the problems haven’t gone unnoticed — even if the solutions aren’t delivered exactly on schedule.