Commercial progress to be unveiled at Global Interposer Technology workshop.
By Herb Reiter
Many readers will be familiar with my extensive background and focus in the emerging field of 3D IC technology, including both 3D stacked die and 2.5 interposer design flows. Now, I am excited to bring my expertise and passion to Silicon Integration Initiative (Si2), where I am now Director of 3D Programs, helping Si2’s members in the Open3D Technical Advisory Board develop practical design flow solutions for broad adoption across the semiconductor industry. The following blog should be of interest to both system and IC designers, so please read on.
If your next system requires higher performance at lower power and must fit into a smaller form-factor, please join us for the 4th Global Interposer Technology (GIT) Workshop at Georgia Tech in Atlanta from Wednesday, Nov. 5 through Friday, Nov 7. You are also welcomed at the Golf Tournament on the 8th.
After attending last year’s GIT workshop, I wrote a blog for 3D InCites and predicted that 2014 will see many more design starts, utilizing interposers.
Over the last 9 months, I have seen my expectations confirmed. Many presentations and panels at conferences outlined real ongoing or completed interposer-based designs, and several manufacturers even presented qualification results for 2.5D-ICs pre-production runs. 2.5D-ICs have proven themselves not just as steppingstones to 3D-ICs, but demonstrated to be a better choice for many applications. Only several memory vendors have introduced “memory cubes” and utilize 3D-IC technology in production now.
Developers of interposer-based solutions jumped at these “memory cubes” right away and mounted them next to their GPU or CPU to BREAK DOWN THE DREADED MEMORY WALL. This allowed them to offer, with their next generation system, much higher performance at lower power dissipation. Here are two high-profile examples of impressive results:
Intel announced, in cooperation with Micron, work on a solution for workstations and high-performance computing at data centers. The project, code-named Knights Landing, will use Hybrid Memory Cubes (HMCs) and offer five times the bandwidth of DDR4, at one-third of the energy, in an optimized package. One of the first applications of this CPU- Memory combination in a package will be the next generation Cray XC supercomputer.
I am certain you realize that these advanced packaging technologies require your team to go through a learning curve and to work closely with partners to minimize cost, risk and development time.
Georgia Tech’s Package Research Center has worked on advanced IC packaging technology for many years. They know the packaging material suppliers well, are familiar with latest equipment capabilities and have proven themselves in cooperation with OSATs, foundries, IDMs and fabless IC vendors as valuable development partners.
Don’t miss the 4th Global Interposer Interposer technology Workshop. It is an opportunity to get to know the experienced Packaging Research Center Team, hear the latest about interposer technology and network with suppliers and power users. More information about this workshop is available here.