Top Stories
Challenges Mount For EUV Masks – Industry is still struggling with defects and have made some progress, but challenges persist for larger masks.
The Upside Of Through-Silicon Vias – TSVs are not like interconnects, and that’s a good thing.
Debate Heats Up Over Bigger Glass – New equipment and materials will be necessary and costly, but the upside is better resolution.
Approaching IP Quality From Many Angles – It takes an ecosystem to ensure IP quality. The IP providers, EDA tool vendors and foundries all play a role.
Executive Briefing: Getting Direct On Litho – Semiconductor Engineering sat down and talked with David Lam, principal of the David Lam Group, an investment and advisory firm.
Multi-Beam Begins To Shine – Single e-beam vendors shift their focus as older approach runs out of steam, but development costs remain high.
Latest News
Manufacturing Bits: Oct. 15 – Better beer; nano-printing invisible materials; enabling DSA.
Inside Japan: The Applied Materials-Tokyo Electron Merger – Analysis: What’s behind the deal. Was it really “now or never?”
Blogs
On The Mark: Applied-TEL Watch – 5 technology areas to track in the wake of the industry’s biggest merger.
Piecing It Together: Standards Watch – The number of standards under consideration is rising, but the number of groups working on those standards is shrinking.
Mentor Musings: Reducing The Tapeout Crunch With Signoff Confidence – Progress is being made in automated fixes during P&R, but most solutions rely on proprietary verification decks.
Cascade Effects: The “Last Simple Node” And the Internet of Things – A huge amount of foundry space built in the last five years will be converted to 28nm.
Viewpoints: SEMI: Following The Yen – A look at the current investments in flash, LED, and MEMS In Japan.
Semico Spin: New World Applications And The Role of IP – Before we witness hockey-stick growth, there are a few challenges to resolve.
Edges Of Darkness: Stanford Photonics In 2013 – Accelerating into X-rays, environment and life-sciences.
Whitepapers
Improving Design Reliability By Avoiding Electrical Overstress – Sophisticated reliability checking, a unified rule deck and integrated debugging can go a long way to preventing device failures.
Tackling Verification Challenges With Interconnect Validation Tool – Complexity involving interconnects is growing as the capacity of SoCs increases, and with that comes a growing verification challenge.
