Traditional low-power verification only validates functional correctness. Power logic and multi-clock logic add new issues.
Reducing power consumption is essential to mobile and handheld application chips where reduced power contributes to longer battery life while minimally impacting performance. Reduced power consumption is achieved by partitioning an ASIC into multiple power domains, then controlling the power of these domains by switching off power or reducing voltage levels. Reduction of power consumption is further complicated by the interdependence of logic between power domains. This logic interdependence requires designers to add isolation, retention, and voltage shifter components at the power domain interfaces.
The addition of power control logic introduces new challenges to both design and verification efforts. The Unified Power Format (UPF) is the IEEE standard format for specifying power domains and power control logic that is added to the RTL design. UPF support is required for all tools in the design and verification process, including simulation, synthesis and physical design. Traditional low power verification only validates the functional correctness of power control logic but does not validate the impact of power logic on multi-clock logic. Designers must additionally validate that power control logic does not introduce new multi-clock issues into their designs.
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