Revenues for semiconductor IP are expected to grow, but the easy money may have already been made. Developing IP is getting tougher on several fronts.
The semiconductor intellectual property (IP) industry is two decades old, but questions are still being asked about what’s wrong with it and what needs to be fixed. Normally these kinds of issues are reserved for fast-moving, young industries, not one that is the backbone of semiconductors.
Design reuse has become an indispensable part of the design of nearly all electronic systems. It is now the largest segment of the EDA industry, and yet the industry is still asking fundamental question about how to make reuse more cost-effective, more efficient and more standardized.
IP developers are struggling to meet increasing demands that are being placed on them, while simultaneously dealing with demographic changes in their markets. Can small IP developers survive? Or will the market continue to shrink until only a few large aggregators exist?
At the Design Automation Conference this year there were several panels, sessions and talks that discussed why such an important part of the semiconductor industry is in such disarray and whether the problem getting better or worse.
IP by the numbers
Jim Feldhan, founder of Semico Research, presented some of the numbers associated with the industry. He said IP is growing faster than semiconductors in general, especially when looked at from a unit perspective. In dollar terms, it is more stable and approaching 50% of the total dollars for semiconductors.
The mix of design starts is expected to change over the next few years with today’s largest category, the performance SoC expected to decline. Part of the slack is taken up by the ‘value SoC,’ which Feldhan says is found in consumer devices such as TVs and home automation, but the biggest area of growth will be ‘basic SoCs’, such as those found in the IoT and industrial applications.
The average number of IP blocks in a design continues to grow and that is creating a large problem for the industry. “Integration costs are growing” he says. “At 14nm, the cost of silicon for a first-time design is $82M, and of that, 35% goes to integrating the IP into the silicon. That rises to 39% of the total costs at 7nm. The costs are more alarming on the software side. At 14nm, the costs are $91M, and 35% of that was going to integrating the software into the design. That will increase to 42% by 7nm.”
With costs that high, and rising that rapidly, you would expect the industry to be on top of it with new tools, methodologies and approaches to help lower those costs. So far that hasn’t happened. “The EDA industry has to create new tools that help to reduce the cost of integration into silicon,” says Feldhan. “We need new tools to simulate the design so that we can reduce the number of wafer shuttles. These are expensive and time-consuming. In the past we designed the chip and threw it over the fence to the software team. You can no longer do this. You have to do more of this up-front.”
Integration problems aside, it would appear as if the IP industry has a few good years ahead of it and can expect to see revenues increase. However, the easy money may have already been made and extracting profit from the development of IP may start getting a lot more difficult. This is driven by changing requirements along various axes.
To compete in the latest devices means working with the foundries, in some cases for years, while a new process technology is being developed. To address the integration issues, more views and more collateral has to be provided with the IP. Diversification of the industry means that IP has to become a lot more customized and each variant will have fewer potential customers. All these are changing the cost/reward equation.
More work to do
To alleviate integration costs means higher quality, more consistency and better integration into existing tools and flows. This all adds up to increased effort for the IP developer. “While there are some standards for IP quality, they aren’t consistent across all foundries and IP providers,” says Lisa Minwell, senior director of marketing for the IP business at eSilicon. “Every IP provider has differences in how they report their characteristics such as how they measure and report power. We see big differences and that makes it difficult to compare IP.”
There also is an explosion in the technology bases for IP, each of which may require special consideration. “You may recall in the days of 130nm and 90nm, foundries had a high-speed flavor and a low-power flavor,” says Kelvin Low, senior director for foundry marketing at Samsung Semiconductor. “This required two sets of IP. Today, this has increased dramatically and requires a more disciplined effort. Consider FD-SOI. This is a single platform capable of wide-ranging applications and can be used for applications ranging from things like IoT up to high-end devices.”
Just keeping track of different versions of IP has become a problem. “From an IP development perspective this means there is large variety of needs on single platform,” says Ranjit Adhikary, vice president of marketing at ClioSoft. “The problem is maintaining so many different versions of the IP. What issues are faced by each customer? Branching of the IP has to be tracked. IP management becomes a complex process and requires a well-defined process.”
In addition to keeping up with the processes technologies and many variants customers are demanding, new types of requirements are being placed on IP, such as security. “The customer base is struggling with security,” says John Koeter, vice president of marketing for IP and prototyping at Synopsys. “They all know they need it but few of them know how to solve this problem? Security is about levels of trust. The base level is hardware. If you cannot uniquely identify and secure your SoC, you cannot build any layer of security on top of that. You must have a closed security perimeter that enables you to uniquely identify your chip and have keys that get certified for that chip.”
While foundries develop the fabrication technology, the process design kits (PDKs) and some IP such as memory bitcells, traditionally they have not been concerned with more generalized IP blocks. “The customers had a lot of ability to build the IP themselves,” says Low. “But this is changing. Today, foundries are expected to play a bigger role in technology preparation and IP building blocks well in advance of when customers require them. This requires different thinking within the foundry.”
“We are engaging earlier and earlier,” says Koeter. “Today, it is not unusual to engage with a foundry partner at 0.1 PDK. Traditionally, companies without big engineering teams were the users of third-party IP, but now even the top tier companies are outsourcing IP. Part of this is because of the number of processes that are coming and the rate of change for various standards is increasing and they are asking what is their value-add?”
More time to revenue
Having to start preparing IP earlier in the process will make life tougher for small IP developers because they don’t have access to the fabs on a trusted partner level and they would have to consume all of those development costs without any hope of a quick return. “At 10nm, PDK 0.1 to 1.0 is typically about a year apart with a 0.5 in between,” says Low. “Development starts with a model based on early development data and prior node trends. Leading customers start design at PDK 0.1 and concrete design starts at 0.5. To get from 0.1 to revenue, lead products go to tapeout on 0.5 PDK and from tapeout to revenue, for mobile is quick at 6-12mos. In all about 18-24 from 0.1 to revenue. For networking and servers, it takes longer. 0.1 to revenue is 36mos or longer.”
Koeter agrees. “We start working at 0.1 and are taping out test chips at 0.5. Our customers are designing their end products in parallel with that. We are seeing a significant number of tapeouts at 0.9 PDK. This is about nine months after 0.1. This has been the case since 28nm.”
The tradeoff here is risk. “After we tapeout the test chips at 0.5, some customers are willing to go ahead before they even see the results from those test chips,” continues Koeter. “They may be planning to do an incremental spin of their chip but they still expect it to be close to production quality. Other customers prefer to wait for a month or two so they can see the results from the test chips.”
When one application was driving the industry, the path forward might have been relatively clear, but today, a plethora of possible driving applications is emerging. “In the past 10 or 20 years, the industry was dominated by the PC and the smart phone,” says Laxman Vemury, vice president of engineering at Lattice Semiconductor. “Now we are seeing self-driving cars, IoT, and these are creating a need for differentiated IP. I expect most of the innovation will come from the smaller providers.”
It does change the focus, however. “We are used to thinking about doing faster, cheaper, better,” says Camille Kokozaki, president of Design Rivers. “Now we have a new paradigm: wider, deeper. That will be where the differentiation comes from. You can create features, you can provide software or you can differentiate in terms of service.”
And for some companies, this is a plus. “There’s an opportunity here as the industry evolves,” says Vemury. “It favors in my mind the individual bootstrap guy. The key is to bring value to the table. You don’t need to invest in 7nm or 10nm to bring value to the industry. Most innovation is coming higher up in the stack. But the higher you go the more need for additional investment.”
Samir Patel, CEO of Sankalp Semiconductor, is concerned about that. “So you’re right, higher in the stack means more opportunities. But what about things that are lower in the stack. If the smaller guys do not participate, there will be fewer options for standard cells such as PCIe. We’ll be left with just the large aggregators.”
Most people are willing to concentrate on the increased possibility that will result from diversity. “There’s a lot of optimization that needs to be thought about,” says Synopsys’ Koeter. “We are tracking 100 to 150 IoT designs and they fall into two major categories. One involves high-end designs such as the Fitbit ,which is probably manufactured in a 40 to 55nm process. This is not your father’s process. It uses an optimized process with embedded flash capabilities. Power matters, and foundries are driving down the voltages to 0.8v. If you take your existing IP and slap an IoT label on it, you will fail. 60% of these design starts are 40 to 55nm. On the other end is the watch— 28nm going to 16/14. It looks like a stripped down apps processor. Cost, power, voltage, these are the drivers.”
Who decides what IP gets developed? “The funding impetus will come from who wants it for final product,” says Patel. “It used to come from the technology side, but today it is being driven more from the applications side. If we are talking about standard-based IP, then the design was done by committee. What you are adding in terms of value is making it silicon proven. If you can add that value, you will succeed.”
“Even if we consider a standard’s based piece of IP, we need all the views,” counters Vemury. “It’s also your support model. Are you just going to provide IP and be done with it, or take them to tapeout? Then you have to go through all the interoperability and standards compliance. How high up do you go in the stack: drivers? Become a trusted partner, not just an IP provider.
There is another change coming that may upset everything we know about IP. “Analog is having a difficult time scaling,” says eSilicon’s Minwell. “DRAM is another example. The use of interposer technology to create a 2.5D chip is now a reality. We are looking at designs that will use chiplets.”
Minwell explains that a chiplet takes IP that has been fully vetted on a prior technology node and uses that directly on an interposer. “We no longer have the high cost of porting that IP to a new technology. Today, we think of IP as embedded and delivered as software, but now IP may be delivered as known good die. This brings in additional IP needs such as managing communication from ASIC to chiplet and back. This trend that hasn’t been looked at fully yet and we have to consider verification, validation etc. It will take time to get it right.”
At least some things never change. “The first thing you have to look at is why you want to design something,” says Design River’s Kokozaki. “Without that you cannot have success. Then you work out the how and then the what. The real opportunity for IP is to think about why this product is necessary and the rest will be easy.”
Adds Vemury: “There really is no such thing as off-the-shelf IP. It always needs changes or customization. People who are willing to do that will find a place for themselves.”
Bridging The IP Divide Part 1
A lot has changed since the emergence of the IP-based methodology and it is currently going through a major update.
Bridging The IP Divide Part 2
The creation of tools and standards for IP integration is progressing at a snail’s pace, but there is hope. New standards and fabrication methodologies may cause a disruption.
IP Business Models In Flux
With so many unknowns about future designs, it’s hard to figure out where to place bets.