Experimentation is replacing a neatly ordered future, but it’s not all bad.
Shrinking features on a chip is no longer the only way forward, and in an increasing number of designs and markets, it is no longer the best way forward.
Power and performance are generally better dealt with using different architectures and microarchitectures, and all of those provide the potential to reduce silicon area (cost). Cramming more transistors on a die and working around leakage current, increased dynamic power, and wires and interconnects that don’t scale, is a growing challenge. Pushing signals through increasingly thin wires requires more power and increases heat, which in turn reduces reliability and causes a slew of physical effects.
There are effective ways to manage all of this, including a wide variety of sophisticated automation tools. The semiconductor engineering market is filled with very smart people with collective skills to solve just about any electrical or mechanical problem that comes along—providing they have enough time and money to solve them. In the past, the profits from complex SoCs in a single market were enough to offset those investments. In the future, it will cost more to solve more problems, and there is no single end market such as computers or smart phones to provide a sufficient return on investment. Booming markets such as automotive may provide big returns in such areas as embedded vision, but the technologies used in vehicles are very different from one function to the next, and from one automaker to the next.
This has massive implications for the semiconductor industry, which explains why there is so much experimentation these days in so many areas. The industry is no longer on autopilot, hopping from one process node to the next. Even the lexicon has changed. There is more talk about Dennard’s Law than Moore’s Law these days, even though they basically point in the same direction.
Semiconductor development is hardly at a standstill, of course. There is much work to be done in many more markets as more things are connected to the Internet and to each other. But the best way forward for many of these markets is no longer a straight line. In some cases, issues such as power can be solved at the same process node using different materials, different techniques such as heterogeneous processing, custom microarchitectures for those cores, and different memory architectures.
Mentor Graphic’ Felix Baum compares it to the hybrid car market, where Toyota, BMW and Chevrolet make plug-in cars with an electric motor and a gasoline engine. Each does it differently, though. The Toyota Prius plug-in uses the electric motor to supplement the gasoline engine. BMW’s i3 uses a gasoline engine for backup. And the Chevy Volt uses the gasoline engine to charge the battery. The analogy is a good one. At least so far, there is no single way to get to different end points.
Advanced packaging is another variable, and one that already is popular in high-performance markets because the throughput to memory across interposers is significantly faster than trying to push signals across a highly congested, integrated planar die. There are significant power savings to be had with advanced packaging schemes because it takes far less power to drive signals through interposers or TSVs than 7nm interconnects. Add FD-SOI into the mix, and the power/performance equation looks even more interesting—or confusing.
There are benefits on the EDA/IP side, as well. All of these moves will add some stability back into the semiconductor IP industry, which is grappling with far too many variations as foundries diverge not only on processes, but on naming conventions, as well. If you had asked a foundry five years ago what would follow 16/14nm, they would agreed it was 10nm. The new answer may be 10nm, 7nm, or maybe even 8nm or 6nm, and there are arguments brewing about who is doing a real 10nm or 7nm. Processes are in flux, which means IP generally has to be revised multiple times as these processes mature. And because they’re different from one foundry to the next, IP has to be developed for each of them. This is not a sustainable model.
This may help explain why power is becoming much more interesting to EDA companies of late. It’s a new opportunity in new markets, where power estimation and modeling need to be automated with much more accuracy. These tools will be important across a wide swath of markets that may never have used these kinds of tools in the past.
But at this point, there is more murkiness than clarity about future directions. Ask any two engineers what moving forward means these days, and you’re likely to get a different answer. That’s probably not an aberration. More likely it’s a sign of fragmentation, and one which will dominate the semiconductor industry over the next few years as new methodologies and approaches are developed, tested, and ultimately refined enough to set new courses for new markets. But along the way, there will be some interesting developments as new ideas are tested, which will be leveraged far beyond this period of uncertainty. And that, ultimately, will be very good for the future of semiconductor engineering.
FinFET Scaling Reaches Thermal Limit
Advancing to the next process nodes will not produce the same performance improvements as in the past.
Thermal Damage To Chips Widens
Heat issues resurface at advanced nodes, raising questions about how well semiconductors will perform over time for a variety of applications.
Power-Centric Chip Architectures
New approaches can lower power, but many are harder to design.
Keeping The Whole Package Cool
Thermal issues become more complex in advanced packaging.
Power Management Heats Up
Thermal effects are now a critical part of design, but how to deal with them isn’t always obvious or straightforward.