Pattern Classification in a Mixed-Signal Circuit Based on Embedded 180-nm Floating-Gate Memory Cell Arrays

Prototype mixed-signal, 28×28-binary-input, 10-output, 3-layer neuromorphic network, based on embedded nonvolatile floating-gate cell arrays redesigned from a commercial 180-nm NOR flash memory

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Source: Cornell University Library. F. Merrikh Bayat, X. Guo, M. Klachko, M. Prezioso, K. K. Likharev, D. B. Strukov
(Submitted on 6 Oct 2016 (v1), last revised 10 Oct 2016 (this version, v2))

“We have designed, fabricated, and successfully tested a prototype mixed-signal, 28×28-binary-input, 10-output, 3-layer neuromorphic network (“MLP perceptron”). It is based on embedded nonvolatile floating-gate cell arrays redesigned from a commercial 180-nm NOR flash memory. The arrays allow precise (~1%) individual tuning of all memory cells, having long-term analog-level retention and low noise. Each array performs a very fast and energy-efficient analog vector-by-matrix multiplication, which is the bottleneck for signal propagation in most neuromorphic networks.

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