Analog Meets Power In Standards Groups

Exclusive: New efforts and approaches seek to widen appeal and usefulness of IC standards.

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While the topic of language Standards might be cringe-worthy for some, there is some noteworthy work underway in this area—particularly where power and analog meet paths.

There are four main standards here:

  • Verilog-A and Verilog-AMS
  • VHDL-AMS
  • SystemC-AMS
  • SystemVerilog-AMS

SystemVerilog-AMS is the newcomer, and while the standard won’t be available for another couple years, the pace of work is picking up.

According to Accellera’s website, “The working group is currently working on alignment of Verilog-AMS with the SystemVerilog work of the IEEE 1800, or inclusion of AMS capabilities in a new “SystemVerilog-AMS” standard. In addition, work is underway to focus on new features and enhancements requested by the community to improve mixed-signal design and verification, as well as to extend SystemVerilog Assertions to Analog and Mixed-Signal designs through the subcommittees.”

But this doesn’t tell the whole story.

“Almost three years ago, in December 2012, the chair of the Accellera Verilog-AMS committee—[Intel Corp.‘s] Scott Little—requested attendance by a few experts in the industry on an effort to integrate Verilog-AMS into SystemVerilog,” said Martin Vlach, chief technologist for analog mixed-signal at Mentor Graphics, and the technical leader of that effort. It didn’t take long to decide that instead of trying to do interoperability work between Verilog-AMS and SystemVerilog, they instead would create a completely new standard, which will be the extension of SystemVerilog to the AMS domain.

“This was strengthened about a year ago when the Accellera board told the Verilog-AMS committee that the Verilog-AMS 2.4 standard that came out recently is the last standard that they would approve,” Vlach said. “Verilog is going to be end-of-lifed either this year or next year because standards have about a 10-year lifespan. SystemVerilog is a complete superset of Verilog, so this is the IEEE 1800 – 2012 [the IEEE naming convention for the SystemVerilog standard]. Verilog-AMS is based on Verilog 2005, and that comes to its end of life also.”

So while Verilog will continue to be used for many years, no formal updates will occur.

The SystemVerilog-AMS group began meeting in April 2013, and progress has been made despite this being a very complicated effort because. Vlach explained that analog engineers who come from the SPICE world in general are not aware of what’s happening in the digital stimulation domain, so they tend to make guesses. The same is true for digital engineers moving into the digital side.

The group is now at the point that it wants to transition the work out of this somewhat select committee. Vlach stressed that it hasn’t been kept secret, but it has not been publicized heavily because the members wanted to get things ironed out first. “We have a white paper and a lot of slides that explain our ideas. We will be publicizing it to the larger Verilog-AMS committee, so we will have some people coming out of that. We will probably involve the people from the SystemVerilog discrete real modeling committee (SV DC). This is the group on the SystemVerilog committee who put together two important concepts in the 2012 standard: user-defined meta-types and interconnect. We have built on these concepts. We have added analog concepts to the underlying SystemVerilog object structures — the net signals and parameters — and we are now adding the SPICE kind to this. We have defined the way of converting values between the discrete domain and the continuous domain.”

The group is also considering submitting SystemVerilog-AMS to IEEE to make a point standard under 1800 – just as VHDL-AMS was a point standard of VHDL.

The reason that power enters into SystemVerilog-AMS is due to the connect modules in Verilog, he explained. “We’ll call them adapters that you adapt between the logic values 0,1, to the analog values. We actually have to know what kind of power has been supplied and we are considering two ways. One of them is UPF-related. So our effort does indeed take into consideration UPF, and the people who write the models for the conversion between logic and analog values will be able to interrogate the UPF power domain and the supply nets in order to do the correct conversion. That is method one, which is related to the standard UPF. The other way is a kind of multiple-voltage source, multi-voltage domain methodology that has been going on for more than a decade. This efforts for the multiple voltage domain have been mostly vendor specific – so all the Big EDA vendors have our own way of doing it.”

The SystemVerilog-AMS group currently includes Cadence, Mentor Graphics, Synopsys, Intel Corp., Qualcomm, Freescale, Dialog Semiconductor and NXP. The group hopes to present SystemVerilog-AMS at DesignCon next March.

Mladen Nizic, engineering director for mixed-signal solutions at Cadence, sees a lot of activity for leveraging standards for functional verification. “That has been proliferating really well in the last couple of years. A lot of that is driven by power as well because as the chips and whole systems get more highly integrated, power is becoming a very important aspect in many of these applications. Now, the systems operate in many different power modes, so verifying these becomes much more difficult.”

He said every power mode adds another set of testbenches and verification that has to be done. “Verification engineers have to actually create the right strategy for how they’re going to verify their chip or their system, and they have to start with a functional verification, very fast simulations. You can’t really afford to run a lot of transistor-level simulations at that level, if any. You need the effective models so you can verify the connectivity is right, that the functionality meets the spec, and the power modes operate correctly because you have blocks that are shutting down. Is the isolation there? And due to presence of analog blocks, running a static power verification like we do in digital is not that easy. It’s not practical. So we have to rely on simulation, but it has to be fast and effective.”

Challenges with choosing a standard
Even if there is a general idea of what needs to be done, the task of determining the right approach and language is particularly challenging. Nizic takes a neutral stance toward language and standards because modeling is flexible. “You can model a lot of things. You can stretch the capability of the language. And, of course, each of these languages has its sweet spot. Part of that is, traditionally, as they have been used. VHDL-AMS has been used predominantly by system and automotive companies, has a lot of legacy, probably some enhancements there as well as libraries available, and has created a sweet spot there. Verilog-A and -AMS is more with chip designers. SystemVerilog, as well. SystemC-AMS is going through another standardization and trying to find its place more in the system level with software and hardware.”

While each of these has its target users, the bottom line is that problems in creating models and setting up methodologies are very similar. “In other words, you have to know what you model and you have to be pragmatic,” he continued. “Model what you need, not what you can. People go overboard and try to write very elaborate models that then slow down and become really not effective. So you have to be careful what you model—model with a purpose. Then as far as the methodology goes, design teams have to be much more careful, because what I often hear from verification managers is that they are given a fixed amount of time and resources to verify and mitigate the risk. ‘Most of the time we can’t run everything that we want to run, so we have to be very prudent in deciding how we structure our verification process to really eliminate risks.’ That’s the whole approach of trying to first functionally verify your design, and then going into some specific electrical characteristics, performance and some of the sign-off verification, as well. With a fixed amount of resources and time, it has to be structured the best way possible to minimize the risk.”

For verifying power, i.e. power behavior — not necessarily electrical characteristics like voltage drop or power consumption — just power modes and power verification, Nizic said Cadence supports power specification formats in conjunction with analog and mixed-signal simulation, and analog behavioral languages.

Once a particular approach is decided upon, the challenges don’t stop, and these happen both on technical and non-technical levels, he observed.

“On the technical front, I have to decide on where I’m going to invest — what language, what library, what I’m going to model, do I have enough skills to do these things? If I’m not using a model-based assertion and metric-based methodology, that’s an initial investment I have to make. It costs time and retraining and resources. I have to justify that investment. So a lot of design and verification managers become convinced after some time, especially after experiencing challenges with traditional methodologies, and they finally move and make the investment and enjoy the benefits after that. The other part is purely organizational. It’s a change. Frankly, that’s often a bigger challenge than technical because it has to be teamwork. There is no single person that can do this. Especially today, with large teams scattered in many places geographically, coordinating all of that and having the right ownership of the modeling, test, development, regressions is a bigger obstacle than the technical side.”

Changing standards process
What’s clear is that change is afoot in the standards world, and it’s an interesting time for EDA standards.

“Traditionally, if you have looked at standards that have come out of Accellera and the EDA standards that have come out of IEEE, the lead and strong backing was coming from EDA vendors,” said Yatin Trivedi, director of standards and interoperability programs at Synopsys. “Now, the chairs of these four standards efforts are with large semiconductor companies, and that’s a change. Some of these larger users are very involved and quite aware that, unless they lead these things, they could be asked to follow a standard that may not be to their liking. So they are actively participating and leading the efforts.”

The EDA industry is also lending a key player to the standards work at the IEEE. Karen Bartleson, senior director, corporate programs and initiatives at Synopsys, has been selected IEEE 2016 president-elect, and 2017 president and CEO. She adds to the IEEE a breadth and depth of knowledge on many aspects of the EDA and semiconductor industries.

Also, interestingly, IEEE recently changed its rules about allowing the community to comment on standards on the ballot in a Public Review forum. With IEEE 1666.1 (SystemC-AMS), the first standard going into ballot also has a public review running simultaneously. [Through the end of this month.]

“To a large extent, the effect of that is that you don’t have to be part of the ballot group,” Trivedi noted. “You can still make a comment. And when the working group ballot committee looks at the ballot comments that come in, they can choose to incorporate the public comment, so this gives an additional source of receiving comments. This brings a much larger community to look at these standards and say, ‘If I were to use this standard, would I be happy about it? Would I be unhappy about it?’ as opposed to, so far, if you are in that relatively small group, only then your voice will be heard and input taken. Involving the whole industry is very important. You can always create a standard for your five friends, but when you involve the whole community it becomes much more usable.”



  • Marq Kole

    The article lists Zilog as one of the participating companies. This is not correct – you are probably referring to Dialog Semiconductor.

    • Jesse Allen

      Thank you! Updated.

  • Kev

    Unfortunately the standards committees at the IEEE for SystemVerilog are “enitity” based, and individuals don’t get to participate unless they are prepared to sign up as entities ($5k+). SV committees are dominated by EDA company representatives from digital verification/simulation groups, who hate all things analog and can’t get their heads around any abstraction more complicated than 0/1/X, let alone concepts like DVFS or body-biasing in FD-SOI.

    As the person who invented the boundary handling mechanism (connect modules) in Verilog-AMS, I know how to make SystemVerilog-AMS work with various interesting levels of abstraction in between the 1/0 and voltage/current levels, but in two decades of working on the committees, there has been practically no improvement in the HDLs’ abilities in this area, and nearly all proposals have been ignored/rejected.

    SV/Verilog-AMS mergers have been announced before, but if anybody actually wants it to work, they’re going to have to sponsor (people like) me to go do it.

    https://www.linkedin.com/in/kevcameronhttps://www.linkedin.com/grp/home?gid=2119051

  • Marq Kole

    As it happens the SystemVerilog-AMS work described in this article is driven from Accellera which is the current owner of the Verilog-AMS standard. That said, the Accellera membership is only open to companies and organizations.

    With respect to the domination of EDA company representatives from digital verification/simulation groups I can state that that is simply not true. There are sufficient representatives from the analog groups, both in the EDA companies as well as from the semiconductor companies involved. As NXP Semiconductors’ representative in the Verilog-AMS standardization committee I am actively involved. I can assure you that AMS simulation at many different abstraction levels is key to our verification efforts so we want to keep a close tab on the developments here. The whole point of working on a SystemVerilog-AMS standard is to overcome the severe limitations of the current Verilog-AMS connect module approach has when it comes to interaction with the digital/system side. For instance, connect modules cannot properly handle a bidirectional net connection that has a tran gate on the digital side. Similarly, insertion of connect modules can change with the design hierarchy applied – even though nothing changes in the design functionality. Resolving issues in AMS design resolution and connect module insertion has proven itself to be a beast – independent of the implementations made by the EDA companies.

    As described in the article the current activities within the team focus on completing a white paper targeted for March 2016. This paper will be outlining the direction of thought and how to overcome the various issues and obstacles in merging the two standards into a new language standard. I’d be interested to hear your comments on the proposals in the paper once published.