Power Aware CDC Verification Of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts

What else needs to be considered with power logic and multi-clock logic.

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Traditional low power verification only validates the functional correctness of power control logic, but it does not validate the impact of power logic on multi-clock logic. We will discuss the effects of advanced low power design on CDC design and verification. This paper describes the new CDC issues caused by the addition of power control logic including isolation cells, retention cells, level shifters, and dynamic voltage scaling. It describes the resolution of these CDC issues by employing netlist analysis, assertions and formal verification, and illustrates these issues and solutions with real life Unified Power Format (UPF) examples and designs.

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