Advanced dynamic power reduction techniques: operand isolation, operand pre-computation, and multi-VDD.
Rapid changes in SoC power issues have forced a rethinking of methodologies throughout the design flow to account for power-related effects. At 65 nanometer process nodes and below, leakage power and dynamic power consumption make it increasingly difficult to meet power budgets. Achieving timing and signal integrity closure is now tightly coupled with power optimization and power net distribution. More importantly, increases in SoC size and speed have brought heat dissipation and reliability issues such as electromigration and IR drop to center stage for a wide range of design applications.
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