The problems have been identified and are being worked on. This is very good news.
I don’t know about you but I am fired up (in a good way) with everything surrounding low power and design at the system level. We are at a point where the challenges are pretty well understood, we can see the way forward in many areas, but what needs to happen next is the evolution of technology that will compel users to adopt the new techniques, which may have yet to be created.
Engineering teams are spending more of their time on power management, even though at this point if they are working at the RTL, they may only be able to make changes for the better up to 10%. Once the technology and tools are available to work at the architectural level, that percentage doubles.
We know there must be consensus on how to capture power information, feeding it into an agreed-upon model so that architectural analysis becomes a reality and not just a bunch of wishful thinking. Of course this is not so easy—not just from a technical perspective, but coming to consensus in the engineering community. It is clear that the few IDMs left in the world want these issues to be worked out and are not shy about spelling out their concerns and desires.
Once we have agreed on the power format, the capabilities of the models themselves must be expanded in order to account for power information, which it lacks today. Then all of this needs to be able to be plugged into virtual platforms for true system-level planning and architectural specification. Ideally, the issue with transactors among various hardware accelerator vendors will be solved too.
I do see some, if not all, of this being addressed today in the working groups within standards efforts. It is an exciting time in the evolution of the industry when a number of technologies will be orchestrated into a grand symphony that allows engineering teams to realize the promise of true power-aware system-level design.
~Ann Steffora Mutschler
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply