Hybrid approach pairs very thin silicon with printed interconnects and sensors.
Flexible electronics have been proposed for a wide variety of applications, from pulse and activity monitoring to electrolyte balance measurements. That makes generalizations difficult, but most proposed devices involve some combination of sensors, a power source, onboard data storage and analysis electronics, and some form of communications for configuration and data transfer.
Flexible electronics offer both cost and usability advantages over their rigid counterparts. (For this reason, this article distinguishes between flexible electronics and other types of wearable electronics, such as smart watches.) Because data from flexible electronics might be used to support treatment decisions for people with chronic illnesses, accurate and consistent measurements are essential. A patch that bends and stretches like skin is more likely to be worn consistently than a larger, bulkier device. Electronics made with printing technology are likely to be less expensive, too, an equally important consideration if the device needs to be disposable for sanitary reasons.
The tradeoff between flexibility and performance becomes apparent very quickly, though. While printable semiconductors have made significant advances in the last several years, they cannot match the capabilities of leading-edge silicon. For this reason, many observers expect flexible electronics to use hybrid technology, pairing very thin silicon logic and communications circuits with printed interconnects, sensors, and possibly power sources.
Such a hybrid integration scheme requires the ability to transfer silicon circuits to a flexible substrate without damage. As Abdullah Alharbi, a graduate student at New York University, explained in a presentation at December’s IEEE Electron Device Meeting, transfer techniques fall into three main categories. The first category, brute force methods, use mechanical and/or chemical polishing to thin the semiconductor. The second, epitaxial layer liftoff, depends on the selective lateral removal of an embedded sacrificial layer, for example by etching.
The third method, is mechanical exfoliation via substrate cracking, also known as spalling. Controlled spalling first deposits a metastable film with high fracture toughness and intrinsic tensile stress onto the substrate. This group, for example, deposited pre-tensioned nickel on top of extremely thin silicon-on-insulator (ETSOI) devices. ETSOI is desirable because it offers low short channel effects, allows designers to use body bias for optimization, and does not require channel doping.
Next, they used a flexible tape to pull the nickel layer until the underlying substrate failed, cracking about 20 microns below the buried oxide. Easily scalable, this is a room temperature process and applicable to any brittle substrate.
Strain engineering is an important feature of leading edge process flows, but little work has been done on strain engineering in flexible devices. With controlled spalling, the semiconductor undergoes residual compressive strain after release from substrate. In GaAs, this strain can be used to tune the band gap. For example, the NYU researchers fabricated flexible GaAs solar cells for energy harvesting, tuning the bandgap to optimize for expected light conditions.
Hybrid electronics are attractive because all-printed electronics are likely to be limited to a few hundred transistors due to both yield limitations and the large areas they require. The best printed circuits have linewidths in the tens of microns. Nevertheless, printed electronics could offer important advantages for extremely cost-sensitive applications such as disposable sensors for medical screening. With a carrier mobility of as much as 12 cm2/V-sec, amorphous indium gallium zirconium oxide (a-IGZO) is comparable to polysilicon and is a leading candidate for n-type printed semiconductors. Unfortunately, according to Imec’s Paul Heremans, efforts to find a complementary p-type semiconductor have had limited success.
The best candidate material so far is SnO, with a best carrier mobility of 4.6 cm2/V-sec. Integration of SnO with a-IGZO in complementary logic has been demonstrated, but results are poor. The shortcomings of SnO include polycrystalline structure and the presence of n-type SnO2 and metallic Sn in the deposited film. Screening of candidates by ab-initio calculus gave (K,Na)2Sn2O3, B6O, and ZrOS as promising potential alternatives. However, in further simulations, amorphization of these materials led to localization of holes. As a result, these materials are unlikely to offer the band-like carrier transport needed for semiconductor devices.
Alternatively, Kuniharu Takei’s group at Osaka Prefecture University used carbon nanotubes and sputtered a-IGZO for p-type and n-type semiconductors, respectively, with Cr/Au electrodes for the source and drain. Polyimide supplied passivation and a strain relaxation layer. The carbon nanotube thin film transistors demonstrated carrier mobility of 9.95 cm2/V-sec, in the ballpark for commercially useful devices. Device channels were 100 microns long by 400 microns wide, leaving much room for future power and area savings via process shrinks.
As is typical at the Electron Device Meeting, the devices discussed here are prototypes and manufacturing proofs of concept. Medical sensors in particular face an especially long road to commercial applications. Still, as these papers showed, technology platforms are emerging to support the many different uses that flexible electronics may find.
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