Questions about how to build future chips fall into three camps.
There are three main options for chipmakers over the course of the next decade. Which option they choose depends upon their individual needs, talents, and how much and what kind of differentiation they believe will matter to them.
The options roughly fall into three categories—fence, bridge or tunnel.
The fence option
Rather than changing anything, the entire ecosystem can stick to what it has perfected over the past 50 years, shrinking features and dealing with problems as they come up, one node at a time. This, of course, limits the effort that goes into new approaches—hence, the fence.
FD-SOI has offered a way to at least delay this decision for a couple of nodes without having to move to double patterning for at least one more node—22nm is the last node where 193nm immersion technology will work using a single pass of the laser, and it’s the last node where finFETs are not required. That means throughput in the foundry in terms of wafers per hour is higher and dynamic power isn’t the dominant issue. It also means design is an almost straight line from 28nm planar CMOS using 2D transistors.
It remains to be seen what happens with FD-SOI at 14nm. Proponents say it’s possible there will be one more generation without finFETs, and by that point commercially viable EUV could be ready to avoid double patterning. Even bulk CMOS could be much simpler at 14nm and 10nm with EUV, and there is enough experience working with finFETs at this point that the learning curve is less steep.
Betting on EUV has been rather one-sided for years, with the semiconductor industry on the losing side of that bet. Still, there is measurable progress being made on two fronts, the power source and the photoresist. That doesn’t mean double patterning goes away for bulk CMOS, but it does mean that multi-patterning can be delayed until 5nm—allowing time to deal with other thorny issues such as RC delay in interconnects and new and softer materials that need to be included to keep electrons from leaking everywhere.
Very big processor companies are betting heavily on the fence option, but they’re quietly—and sometimes not so quietly—investigating other options.
The tunnel option
Regardless of whether big chipmakers can continue down the ITRS roadmap for another couple process nodes, they will need new transistor structures. There are plenty of them—carbon nanotubes, lateral and vertical nanowire FETs, and tunnel FETs—and they all address the problem of moving electrons from point A to point B at maximum speed with minimal resistance and capacitance.
Tunneling is one of the more interesting developments here, in part because it may be more efficient to move electrons through barriers rather than over them. The big advantage is lower current swings and therefore lower power. But it’s also a new transistor structure. No matter how good ideas look in a lab, they look much different when they’re packed together on a die and there are all sorts of unanticipated physical and, at 7nm, quantum effects.
The advantage of TFETs is they can use the same materials as finFETs or MOSFETs. With nanowires, there are questions about manufacturability that have not been answered yet, such as what materials are needed to move electrons through increasingly narrow wires and whether those materials are available, difficult to work with commercially, and how much they will add to the cost.
While this is an interesting way to build a transistor, though, moving electrons across chips is another matter. Silicon photonics may play an interesting and necessary role here if III-V materials don’t work out as planned.
Building a bridge
Option No. 3 is the bridge approach, whether it’s an interposer, through-silicon via, or some other proprietary bridge. Given the recent activity at SEMICON Taiwan (see related story), it’s hard to ignore the amount of enthusiasm this is generating from OSATs.
Foundries and equipment makers like this option, as well. For one thing, it provides a growth path that will work no matter how small features are shrunk on processor and memory platforms, and it ensures their investments in new technology will be used for many generations to come. The cost of developing new equipment and the cost of equipping fabs with the latest equipment is enormous, and if transistor structures and materials need to change every new node that cost could go dramatically higher and create new bottlenecks.
That makes 2.5D and 3D architectures, as well as fan-outs, much more interesting, and that interest is beginning to catch fire as a way of generating unique chips for the IoT using standard components and connections.
While it’s easy to see these approaches as either/or, the reality is that all of them might be used in the same chip or package. A 7nm processor with a very uniform layout connected to a memory stack and sensors in an IoT device, or to an FPGA or custom 28nm FD-SOI chip in a data center, is almost beyond comprehension these days.
But just as it takes an ecosystem to make a chip faster, cheaper and lower power, it will take an ecosystem to define the next phase of chipmaking—at the right cost point, with the right performance and the right power/energy efficiency. It’s very likely that not all of the components in that chip will be on the same piece of silicon, use the same process technology, and that signals won’t use the same copper interconnects that have been standard since 130nm.